公开(公告)号：JP2001013670A

公开(公告)日：2001-01-19

申请号：JP2000160870

申请日：2000-05-30

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： SHAHIDO BUTTO ,  KAMIZU FARAHAPUURU ,  HAFFNER HENNING ,  MARK A RABIN ,  LAAS W LIEBMANN ,  DONALD J SAMUELS

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G06F17/50 ,  H01L21/027 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for enhancing the efficiency of the proximity correction of a pattern forming process in terms of given chip layout design, and constitution therefor. SOLUTION: This method includes a step G01 for describing the pattern forming process in accordance with at least one layout parameter, a step G03 for making the distribution of at least one parameter discrete, a step G05 for providing an error correction table linking the correction of layout with at least one parameter and a step G06 for correcting the layout by applying correction in the table to the layout at least once.

公开(公告)号：WO0142996A3

公开(公告)日：2002-02-14

申请号：PCT/US0033146

申请日：2000-12-06

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANSFIELD SCOTT M ,  LIEBMANN LARS W ,  BUTT SHAHID ,  HAFFNER HENNING

IPC: G03F1/00 ,  G03F1/36 ,  G03F7/20 ,  G06F17/50

CPC classification number: G03F1/36 ,  G03F7/70441

Abstract: A semiconductor device can be fabricated using a photomask that has been modified using an assist feature design method based on normalized feature spacing. Before the device can be fabricated, a layout of original shapes is designed (402). For at least some of the original shapes, the width of the shape and a distance to at least one neighboring shape are measured (404). A modified shape can then be generated by moving edges of the original shape based on the width and distance measurements (406). This modification can be performed on some or all of the original shapes (408). For each of the modified shapes, a normalized space and correct number of assist features can be computed (410). The layout is then modified by adding the correct number of assist features in a space between the modified shape and the neighboring shape (412). This modified layout can then be used in producing a photomask, which can in turn be used to produce a semiconductor device.

Abstract translation: 可以使用已经使用基于归一化特征间隔的辅助特征设计方法修改的光掩模来制造半导体器件。 在可以制造设备之前，设计原始形状的布局（402）。 对于至少一些原始形状，测量形状的宽度和至少一个相邻形状的距离（404）。 然后可以通过基于宽度和距离测量来移动原始形状的边缘来生成修改的形状（406）。 可以对部分或全部原始形状执行该修改（408）。 对于每个修改的形状，可以计算归一化空间和正确数量的辅助特征（410）。 然后通过在修改的形状和相邻形状之间的空间中添加正确数量的辅助特征来修改布局（412）。 然后，该修改后的布局可用于制造光掩模，光掩模又可用于制造半导体器件。

公开(公告)号：WO0163648A9

公开(公告)日：2002-10-24

申请号：PCT/US0105373

申请日：2001-02-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  EINSPRUCH FRED L ,  HAFFNER HENNING ,  THOMAS ALAN C

IPC: H01L23/525 ,  G03F1/14

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a photolithography mask for use in creating an electrical fuse on a semiconductor structure comprises initially determining a pattern for a desired electrical fuse, with the pattern including a fuse portion of substantially constant width except for a localized narrowed region of the fuse portion at which the electrical fuse is designed to blow. The method then includes providing a photolithography mask substrate and creating on the photolithography mask substrate a fuse mask element adapted to absorb transmission of an energy beam. The fuse mask element has a first mask portion of substantially constant width corresponding to the desired electrical fuse pattern portion of substantially constant width, and a second mask portion corresponding to the localized narrowed region of the fuse portion. The second mask portion comprises either an additional mask element spaced from the first mask portion, a narrowed width portion, or a gap in the first mask portion. The second mask portion is of a configuration sufficient to create a latent image of the electrical fuse pattern, including the localized narrowed region of the fuse portion at which the electrical fuse is designed to blow, upon passing the energy beam through the photolithography mask and onto a resist layer. Preferably, the fuse portion of substantially constant width on the determined fuse pattern has a design width less than about 0.25 mu m, and wherein the localized narrowed region of the fuse portion has a design width less than the design width of the fuse portion.

Abstract translation: 制造用于在半导体结构上形成电熔丝的光刻掩模的方法包括：首先确定所需电熔丝的图案，其中所述图案包括基本恒定宽度的熔丝部分，除了熔丝部分的局部变窄区域 电熔丝被设计在其上。 该方法然后包括提供光刻掩模基板，并在光刻掩模基板上产生适于吸收能量束透射的熔丝屏蔽元件。 熔丝掩模元件具有对应于基本恒定宽度的期望电熔丝图案部分的基本恒定宽度的第一掩模部分和对应于熔丝部分的局部变窄区域的第二掩模部分。 第二掩模部分包括与第一掩模部分间隔开的附加掩模元件，第一掩模部分中的窄宽度部分或间隙。 第二掩模部分具有足以产生电熔丝图案的潜像的构造，包括将电熔丝设计成熔断部分的熔断部分的局部变窄区域，以使能量束通过光刻掩模并进入 抗蚀剂层。 优选地，确定的熔丝图案上的基本上恒定的宽度的熔丝部分具有小于约0.25μm的设计宽度，并且其中熔丝部分的局部变窄区域具有小于熔丝部分的设计宽度的设计宽度。

公开(公告)号：WO0137320A3

公开(公告)日：2001-12-06

申请号：PCT/US0030404

申请日：2000-11-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： REITH ARMIN M ,  HSU LOUIS ,  HAFFNER HENNING ,  LEHMANN GUNTHER

IPC: G06F17/50 ,  H01L21/02 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC classification number: H01L28/40 ,  H01L27/10861 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.

Abstract translation: 使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。 该方法将自动或手动生成光刻填充图案与电容器的形成相结合。 根据该方法，当芯片布局即将完成时，芯片上剩余的空余空间由布局工具识别。 然后，最近的电源网络被提取。 所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。 然后空的空间被分配适当的去耦电容。 通过该方法产生的去耦电容适用于降低噪声的VLSI电源。

公开(公告)号：WO0163648A3

公开(公告)日：2002-04-18

申请号：PCT/US0105373

申请日：2001-02-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  EINSPRUCH FRED L ,  HAFFNER HENNING ,  THOMAS ALAN C

IPC: H01L23/525 ,  G03F1/14

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a photolithography mask for use in creating an electrical fuse on a semiconductor structure comprises initially determining a pattern for a desired electrical fuse, with the pattern including a fuse portion of substantially constant width except for a localized narrowed region of the fuse portion at which the electrical fuse is designed to blow. The method then includes providing a photolithography mask substrate and creating on the photolithography mask substrate a fuse mask element adapted to absorb transmission of an energy beam. The fuse mask element has a first mask portion of substantially constant width corresponding to the desired electrical fuse pattern portion of substantially constant width, and a second mask portion corresponding to the localized narrowed region of the fuse portion. The second mask portion comprises either an additional mask element spaced from the first mask portion, a narrowed width portion, or a gap in the first mask portion. The second mask portion is of a configuration sufficient to create a latent image of the electrical fuse pattern, including the localized narrowed region of the fuse portion at which the electrical fuse is designed to blow, upon passing the energy beam through the photolithography mask and onto a resist layer. Preferably, the fuse portion of substantially constant width on the determined fuse pattern has a design width less than about 0.25 mu m, and wherein the localized narrowed region of the fuse portion has a design width less than the design width of the fuse portion.

Abstract translation: 制造用于在半导体结构上形成电熔丝的光刻掩模的方法包括：首先确定用于期望的电熔丝的图案，其中该图案包括除了熔丝部分的局部变窄的区域之外基本恒定宽度的熔丝部分 在此电熔丝被设计为吹塑。 该方法然后包括提供光刻掩模衬底并且在光刻掩模衬底上产生适于吸收能量束的透射的熔丝掩模元件。 熔丝掩模元件具有基本恒定宽度的第一掩模部分和与熔丝部分的局部缩窄区域对应的第二掩模部分，第一掩模部分对应于基本恒定宽度的期望电熔丝图案部分。 第二掩模部分包括与第一掩模部分隔开的另外的掩模元件，变窄的宽度部分或第一掩模部分中的间隙。 第二掩模部分具有足以产生电熔丝图案的潜像的配置，该电图案包括保险丝部分的局部变窄的区域，在电熔丝被设计成在该区域处被吹过，在通过能量束通过光刻掩模并且到 抗蚀剂层。 优选地，在所确定的熔丝图案上具有基本恒定宽度的熔丝部分具有小于约0.25μm的设计宽度，并且其中熔丝部分的局部变窄区域具有小于熔丝部分的设计宽度的设计宽度。

公开(公告)号：WO0184237A3

公开(公告)日：2002-06-27

申请号：PCT/US0111318

申请日：2001-04-06

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： BUTT SHAHID ,  HAFFNER HENNING ,  FRANKOWSKY BEATE

IPC: G03F1/00 ,  G03F1/14

CPC classification number: G03F1/68 ,  G03F1/36 ,  G03F1/44 ,  Y10S977/839 ,  Y10S977/887

Abstract: A method of fabricating a semiconductor device is outlined in Figure 3. An ideal (or desired) pattern of a layer of the semiconductor device is designed (305). A first pass corrected pattern is then derived by correcting the ideal patterns for major effects, e.g., aerial image effects (315, 320). A second pass corrected pattern is then derived by correcting the first pass corrected patterns for remaining errors (340). The second pass corrected pattern can be used to build a photomask (345). The photomask can then be used to produce a semiconductor device, such a memory chip or logic chip (350).

Abstract translation: 制造半导体器件的方法在图3中概述。设计半导体器件层的理想（或期望的）图案（305）。 然后通过校正主要效果（例如，空中影像效果）的理想图案（315,320）来导出第一通过校正图案。 然后通过校正用于剩余错误的第一通过校正图案来导出第二遍校正图案（340）。 第二遍校正图案可用于构建光掩模（345）。 然后可以使用光掩模来制造半导体器件，诸如存储芯片或逻辑芯片（350）。

公开(公告)号：DE60030467D1

公开(公告)日：2006-10-12

申请号：DE60030467

申请日：2000-11-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： REITH M ,  HSU LOUIS ,  HAFFNER HENNING ,  LEHMANN GUNTHER

IPC: G06F17/50 ,  H01L21/00 ,  H01L21/02 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.

公开(公告)号：DE60030820D1

公开(公告)日：2006-11-02

申请号：DE60030820

申请日：2000-10-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HAFFNER HENNING ,  HOENIGSCHMID HEINZ ,  SAMUELS DONALD J

IPC: G03F7/20 ,  G03F1/00

Abstract: A method, and a system for employing the method, for providing a modified optical proximity correction (OPC) for correcting distortions of pattern lines on a semiconductor circuit wafer. The method comprises producing a mask having one or more pattern regions, and producing the semiconductor circuit wafer from the mask. The pattern regions include one or more non-edge pattern regions located adjacent to other of the non-edge pattern regions on the mask. The pattern regions further include one or more edge pattern regions located at or near an area on the mask not having the other non-edge pattern regions. The edge pattern regions have widths calculated to minimize the variance in dimensions between one or more pattern lines on the semiconductor circuit wafer formed from them and one or more pattern lines on the semiconductor circuit wafer formed from the non-edge pattern regions. The distances between any two of the pattern regions are calculated to minimize the variance in dimensions between the one or more pattern lines formed from the edge pattern regions and the one or more pattern lines formed from the non-edge pattern regions. The above producing step includes producing the semiconductor circuit wafer from the mask having the pattern lines formed from the non-edge pattern regions and having the pattern lines formed from the edge pattern regions, where the pattern lines formed from the non-edge regions are permitted to differ in distances between them.

公开(公告)号：DE60030467T2

公开(公告)日：2007-05-03

申请号：DE60030467

申请日：2000-11-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： REITH M ,  HSU LOUIS ,  HAFFNER HENNING ,  LEHMANN GUNTHER

IPC: G06F17/50 ,  H01L21/00 ,  H01L21/02 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.