公开(公告)号：WO0198563A3

公开(公告)日：2002-05-30

申请号：PCT/US0119077

申请日：2001-06-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： TEWS HELMUT HORST ,  FALTERMEIR JOHNATHAN E ,  MALIK RAJEEV ,  HEENAN CAROL ,  GLUSCHENKOV OLEG

IPC: C30B29/06 ,  C30B33/00 ,  H01L21/28 ,  H01L21/316 ,  H01L21/762 ,  H01L29/51

CPC classification number: H01L21/28185 ,  C30B29/06 ,  C30B33/00 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02337 ,  H01L21/28176 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/76202 ,  H01L29/513 ,  H01L29/518 ,  Y10S438/973

Abstract: A method for forming an oxide of substantially uniform thickness on at least two crystallographic planes of silicon, in accordance with the present invention, includes providing a substrate (step 100) where surfaces have at least two different crystallographic orientations of the silicon crystal (step 102). Atomic oxygen (O) is formed for oxidizing the surfaces (step 106). An oxide is formed (step 108) on the surfaces by reacting the atomic oxygen with the surfaces to simultaneously form a substantially uniform thickness of the oxide on the surfaces.

Abstract translation: 根据本发明，在硅的至少两个结晶平面上形成基本均匀厚度的氧化物的方法包括提供其中表面具有硅晶体的至少两个不同晶体取向的衬底（步骤100）（步骤102 ）。 形成氧化表面的原子氧（O）（步骤106）。 通过使原子氧与表面反应，在表面上形成氧化物（步骤108），同时在表面上形成基本均匀的氧化物厚度。

公开(公告)号：WO0195391A8

公开(公告)日：2002-03-28

申请号：PCT/US0117927

申请日：2001-06-01

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NESBIT LARRY ,  MCSTAY IRENE LENNOX ,  RADENS CARL ,  TEWS HELMUT HORST ,  DIVAKARUNI RAMA ,  MANDELMAN JACK

IPC: H01L21/8242

CPC classification number: H01L27/10861 ,  H01L27/10867

Abstract: A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner (81) is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer (79). A layer of amorphous silicon (83) is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist (83) is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar (89) along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.

Abstract translation: 一种在存储沟槽DRAM单元的存储沟槽中形成相对薄的均匀绝缘环的方法。 首先在硅衬底中形成DRAM沟槽。 然后，氮化物衬垫（81）沉积在硅沟槽壁上。 氮化物衬垫可以直接沉积在硅壁上或下面的氧化物层（79）上。 然后在氮化物衬垫上沉积一层非晶硅（83）。 在非晶硅的氧化表面上沉积氮化硅层。 在沟槽的下部形成抗蚀剂（83），去除非晶硅顶部的露出的氮化硅层，使非晶硅层的上部露出。 然后，非晶硅层的上部被氧化，以便沿沟槽的整个圆周形成相对较薄的均匀的环（89）。 非晶硅层下面的氮化物衬垫增强了非晶硅层的厚度均匀性，从而提高了所得氧化物环的均匀性。 氮化物衬垫还用于在非晶硅层的氧化期间限制硅沟槽壁的横向氧化。 在套环下面的氮化物衬垫在电池操作中也有效地控制在衬套 - 衬底界面处的电池电荷。

公开(公告)号：WO0199185A3

公开(公告)日：2002-03-28

申请号：PCT/US0119576

申请日：2001-06-19

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  LEE BRIAN S ,  MICHAELIS ALEXANDER ,  KUDLEKA STEPHAN ,  SCHROEDER UWE

IPC: H01L21/8242

CPC classification number: H01L27/10864 ,  H01L27/10876

Abstract: A method of forming a vertically-oriented device such as a DRAM storage all with a trench capacitor under a vertical transistor, using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a poertion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.

Abstract translation: 使用选择性湿法蚀刻仅在沟槽中除去一部分侧壁，以及由其形成的器件，在垂直晶体管下，用沟槽电容器形成诸如DRAM存储器的垂直取向器件的方法。 虽然沟槽周边（例如，隔离环304）的作用被掩模（例如，多晶硅318）保护，但是暴露部分被选择性地湿蚀刻以从沟槽的暴露部分移除所选择的晶面，留下平坦的基板 侧壁（324）与单晶面。 单侧垂直沟槽晶体管可以形成在平坦侧壁上。 形成在单晶平面上的晶体管的垂直栅极氧化物（例如二氧化硅330）在晶体管沟道上基本上是均匀的，从而降低了泄漏的机会和从器件到器件的一致的阈值电压。 此外，沟槽加宽大大降低，从而在单面掩埋带接合器件布局中将器件增加到器件隔离距离。

公开(公告)号：WO0197265A2

公开(公告)日：2001-12-20

申请号：PCT/US0117442

申请日：2001-05-31

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  LEE BRIAN S ,  HOEPFNER JOACHIM

IPC: H01L21/02 ,  H01L21/223 ,  H01L21/8242 ,  H01L21/32 ,  H01L27/108

CPC classification number: H01L27/1087 ,  H01L21/2236 ,  H01L28/84

Abstract: A method of doping trench sidewall and hemispherical-grained silicon in deep trench cells to increase surface area and storage capacitance while avoiding deformation of trenches and hemispherical-grained silicon, comprising: a) Etching a deep trench structure by reactive ion etching; b) Forming a LOCOS collar in an upper portion of the trench over a conformal layer of a silicon containing material, the collar leaving a lower portion of the trench exposed; c) Depositing a film of hemispherical-grained silicon (HSG -Si) at sidewalls of the deep trench; d) Plasma doping the hemispherical-grained silicon; and e) Depositing a node dielectric and filling the trench with polysilicon.

Abstract translation: 一种在深沟槽电池中掺杂沟槽侧壁和半球晶硅的方法，以增加表面积和存储电容，同时避免沟槽和半球形硅的变形，包括：a）通过反应离子蚀刻蚀刻深沟槽结构; b）在含硅材料的保形层上的沟槽的上部形成LOCOS环，所述套环留下暴露的沟槽的下部; c）在深沟槽的侧壁处沉积半球形硅（HSG-Si）的膜; d）等离子体掺杂半球形硅; 以及e）沉积节点电介质并用多晶硅填充沟槽。

公开(公告)号：WO0199162A3

公开(公告)日：2002-07-18

申请号：PCT/US0119882

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： MICHAELIS ALEXANDER ,  TEWS HELMUT HORST ,  KUDELKA STEPHAN ,  GRUENING ULRIKE ,  BEINTNER JOCHEN ,  SCHROEDER UWE

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/04 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/28211 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/045 ,  H01L29/42368 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of using a selective etch to provide a desired crystal plane orientation on the sidewalls of a deep trench located in a semiconductor substrate, and the device formed therefrom. Preferably, a crystal plane sidewall (212) is used for the channel region, and crystal planes (216) are used in the corner regions of the trench. Gate oxidation may then be performed such that the oxide is thicker in the corner regions (222) than on the oxide (218, 220) on the primary sides of the trench, resulting in self isolation of the corner areas from the transistor channel/active area (224). In addition, the structure is relatively insensitive to active area/deep trench misalignment.

Abstract translation: 一种使用选择性蚀刻以在位于半导体衬底中的深沟槽的侧壁上提供期望的晶面取向的方法和由其形成的器件。 优选地，在沟道区域中使用<100>晶面侧壁（212），并且在沟槽的拐角区域中使用<110>晶面（216）。 然后可以执行栅极氧化，使得在角区域（222）中的氧化物比在沟槽的初级侧上的氧化物（218,220）上更厚，导致拐角区域与晶体管沟道/活性物质的自我隔离 区域（224）。 此外，该结构对有源区/深沟槽未对准相对不敏感。

公开(公告)号：WO0191180A3

公开(公告)日：2002-07-18

申请号：PCT/US0115757

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  LEE BRIAN S ,  MICHAELIS ALEXANDER ,  SCHROEDER UWE ,  KUDELKA STEPHEN

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L27/10864 ,  H01L21/76237 ,  H01L21/823487 ,  H01L27/10841 ,  H01L27/10867

Abstract: A system and method of forming an electrical connection (142) to the interior of a deep trench (104) in an integrated circuit utilizing a low-angle dopant implantation (114) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate (110) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material (120) overlying or in the trench, leaving a self-aligned mask (122) covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped and undoped regions, may be used to create the mask. The self-aligned mask then allows for the removal of selective portions of the materials in the trench so that a vertical trench transistor and a buried strap may be formed on only one side of the trench.

Abstract translation: 使用低角度掺杂剂注入（114）在集成电路中形成到深沟槽（104）的内部的电连接（142）的系统和方法，以在沟槽上产生自对准掩模。 电连接优选地将沟槽电容器的内板（110）连接到垂直沟槽晶体管的端子。 低角度注入工艺与低纵横比掩模结构相结合，通常能够仅掺杂覆盖或在沟槽中的材料的一部分。 然后可以在掺杂区域和未掺杂区域之间选择性地对材料进行处理步骤，例如氧化。 然后可以使用诸如蚀刻工艺的另一工艺步骤来去除覆盖在沟槽中或沟槽中的部分材料（120），留下覆盖沟槽的一部分的自对准掩模（122），并且其余部分 沟槽暴露进一步加工。 或者，可以使用仅在掺杂区域和未掺杂区域之间具有选择性的蚀刻工艺来产生掩模。 自对准掩模然后允许去除沟槽中的材料的选择性部分，使得可以仅在沟槽的一侧上形成垂直沟槽晶体管和掩埋带。

公开(公告)号：WO0189284A3

公开(公告)日：2002-05-30

申请号：PCT/US0115896

申请日：2001-05-16

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  MICHAELIS ALEXANDER ,  KUDELKA STEPHEN ,  SCHROEDER UWE ,  GRUENING ULRIKE

IPC: H01L21/8242

CPC classification number: H01L27/10861

Abstract: A method of using at least two insulative layers to form the isolation collar of a trench capacitor, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide 116) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer (114) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate (120) doping.

Abstract translation: 使用至少两个绝缘层形成沟槽电容器的隔离环的方法，以及由其形成的器件。 第一层优选是形成在沟槽衬底侧壁上的氧化物（例如，二氧化硅116），并且通过TEOS，LOCOS或组合的TEOS / LOCOS工艺形成。 优选地，TEOS工艺和LOCOS工艺都用于形成第一层。 第二层优选是形成在氧化物层上的氮化硅层（114）。 多层用作沟槽的隔离环叠层。 第二层的掺杂剂渗透阻挡性质允许电介质套管叠层用作后续掩埋板（120）掺杂的自对准掩模。

公开(公告)号：WO0182333A3

公开(公告)日：2002-01-24

申请号：PCT/US0110919

申请日：2001-04-04

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  LEE BRIAN S ,  GRUENING ULRIKE

IPC: H01L21/28 ,  H01L21/8242 ,  H01L29/04

CPC classification number: H01L21/28211 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/28238 ,  H01L27/10864 ,  H01L27/10873 ,  H01L29/045

Abstract: Improved process for preparing vertical transistor structures in DRAMs, in which the trench top oxide separates the bottom storage capacitor from the switching transistor, and in which the upper part of the trench contains the vertical transistor at its side wall, to obtain homogeneous gate oxidation at all different crystal planes inside the trench so that homogeneous thickness is independent of crystal orientation comprising: a) subjecting a wafer trench side wall to ion bombardment (20) for a period sufficient to generate an amorphous layer (22) on the side wall; and b) heating the wafer resulting from step (a) in an oxidizing atmosphere to cause oxidation and recrystallization of the amorphous layer.

Abstract translation: 在DRAM中制备垂直晶体管结构的改进方法，其中沟槽顶部氧化物将底部存储电容器与开关晶体管分离，并且其中沟槽的上部在其侧壁处包含垂直晶体管，以获得均匀的栅极氧化 沟槽内的所有不同的晶面，使得均匀的厚度与晶体取向无关，包括：a）使晶片沟槽侧壁进行离子轰击（20）足以在侧壁上产生非晶层（22）的时间; 和b）在氧化气氛中加热由步骤（a）得到的晶片，以引起非晶层的氧化和再结晶。

公开(公告)号：DE60037443D1

公开(公告)日：2008-01-24

申请号：DE60037443

申请日：2000-10-13

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  LEE BRIAN

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/318 ,  H01L21/8242 ,  H01L27/108

Abstract: A method of manufacturing a capacitor is provided where at least a portion of a silicon surface is amorphized. The amorphized silicon surface is then subjected to an annealing process to form hemispherical silicon grains (HSG) from the amorphized portion of the silicon surface to form at least a portion of a first electrode of the capacitor. A capacitor dielectric is then formed over the hemispherical silicon grains. A second electrode is then formed over the capacitor dielectric.

公开(公告)号：DE10261330A1

公开(公告)日：2003-08-14

申请号：DE10261330

申请日：2002-12-27

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  KUDELKA STEPHAN P ,  SCHROEDER UWE ,  MCSTAY IRENE LENNOX ,  RAHN STEPHEN

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8242

Abstract: In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not shrink with decreasing groundrule/cell size, comprising:a) providing a semiconductor substrate having a collar region and an adjacent region below the collar region, the collar region having SiO deposited thereon;b) depositing a SiN liner on said collar region and on the region below the collar;c) depositing a layer of a-Si on the SiN liner to form a micromask;d) subjecting the structure from step c) to an anneal/oxidation step under a wet environment at a sufficient temperature to form a plurality of oxide dot hardmasks;e) subjecting the SiN liner to an etch selective to SiO;f) subjecting the structure from step e) to a Si transfer etch using a chemical dry etch (CDE) selective to SiO to create rough Si surface;g) stripping SiO and the SiN; and forming a node and collar deposition.