公开(公告)号：WO0198563A3

公开(公告)日：2002-05-30

申请号：PCT/US0119077

申请日：2001-06-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： TEWS HELMUT HORST ,  FALTERMEIR JOHNATHAN E ,  MALIK RAJEEV ,  HEENAN CAROL ,  GLUSCHENKOV OLEG

IPC: C30B29/06 ,  C30B33/00 ,  H01L21/28 ,  H01L21/316 ,  H01L21/762 ,  H01L29/51

CPC classification number: H01L21/28185 ,  C30B29/06 ,  C30B33/00 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02337 ,  H01L21/28176 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/76202 ,  H01L29/513 ,  H01L29/518 ,  Y10S438/973

Abstract: A method for forming an oxide of substantially uniform thickness on at least two crystallographic planes of silicon, in accordance with the present invention, includes providing a substrate (step 100) where surfaces have at least two different crystallographic orientations of the silicon crystal (step 102). Atomic oxygen (O) is formed for oxidizing the surfaces (step 106). An oxide is formed (step 108) on the surfaces by reacting the atomic oxygen with the surfaces to simultaneously form a substantially uniform thickness of the oxide on the surfaces.

Abstract translation: 根据本发明，在硅的至少两个结晶平面上形成基本均匀厚度的氧化物的方法包括提供其中表面具有硅晶体的至少两个不同晶体取向的衬底（步骤100）（步骤102 ）。 形成氧化表面的原子氧（O）（步骤106）。 通过使原子氧与表面反应，在表面上形成氧化物（步骤108），同时在表面上形成基本均匀的氧化物厚度。

公开(公告)号：SG172678A1

公开(公告)日：2011-07-28

申请号：SG2011041001

申请日：2008-12-03

Applicant: GLOBALFOUNDRIES SG PTE LTD ,  IBM ,  INFINEON TECHNOLOGIES CORP ,  SAMSUNG ELECTRONICS CO LTD

Inventor： WOH LAI CHUNG ,  WEE TEO LEE ,  PING LIU JIN ,  GLUSCHENKOV OLEG ,  UTOMO HENRY K ,  MADAN ANITA ,  LOESING RAINER ,  JIN-PING HAN ,  HYUNG-YOON CHOI

Abstract: INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONSAn integrated circuit system that includes: providing a Pl-ET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer.Fig. 8

公开(公告)号：SG153032A1

公开(公告)日：2009-06-29

申请号：SG2008089690

申请日：2008-12-03

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  INFINEON TECHNOLOGIES CORP ,  SAMSUNG ELECTRONICS CO LTD

Inventor： WOH LAI CHUNG ,  WEE TEO LEE ,  PING LIU JIN ,  GLUSCHENKOV OLEG ,  UTOMO HENRY K ,  MADAN ANITA ,  LOESING RAINER ,  JIN-PING HAN ,  YOON CHOI HYUNG

Abstract: An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer.

公开(公告)号：EP1927128A4

公开(公告)日：2009-01-28

申请号：EP06804017

申请日：2006-09-22

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/51

CPC classification number: H01L29/512 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

Abstract: The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i-e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, and the first gate oxide is higher k than the second gate oxide or vice-versa.

公开(公告)号：EP1382064A4

公开(公告)日：2008-05-07

申请号：EP01987463

申请日：2001-12-27

Applicant: IBM

Inventor： DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  HEDGE SURYANARAYAN G ,  KAPLAN RICHARD ,  KHARE MUKESH

IPC: H01L21/3205 ,  H01L29/786 ,  H01L21/265 ,  H01L21/28 ,  H01L21/31 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28247 ,  H01L29/42368 ,  H01L29/4941

Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners of a Si-containing transistor, and exposing the transistor including implanted transistor gate corners to an oxidizing ambient. The ions employed in the implant step include Si; non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, C1, He, Ar, Kr, and Xe; and mixtures thereof.

公开(公告)号：EP2108192A4

公开(公告)日：2009-12-30

申请号：EP07855285

申请日：2007-12-20

Applicant: IBM

Inventor： LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

IPC: H01L27/10 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

公开(公告)号：EP1683187A4

公开(公告)日：2008-08-27

申请号：EP04810633

申请日：2004-11-09

Applicant: IBM

Inventor： DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/7845 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28247 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

公开(公告)号：EP1864319A4

公开(公告)日：2009-11-18

申请号：EP06748845

申请日：2006-03-29

Applicant: IBM

Inventor： BELYANSKY MICHAEL P ,  GLUSCHENKOV OLEG ,  LI YING ,  MALLIKARJUNAN ANUPAMA

IPC: H01L21/26

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/45523 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method for increasing the level of stress for amorphous thin film stressors by means of modifying the internal structure of such stressors is provided. The method includes first forming a first portion of an amorphous film stressor material on at least a surface of a substrate, said first portion having a first state of mechanical strain defining a first stress value. After the forming step, the first portion of the amorphous film stressor material is densified such that the first state of mechanical strain is not substantially altered, while increasing the first stress value. In some embodiments, the steps of forming and densifying are repeated any number of times to obtain a preselected and desired thickness for the stressor.

公开(公告)号：EP1825509A4

公开(公告)日：2009-04-15

申请号：EP05853786

申请日：2005-12-13

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

公开(公告)号：EP1588403A4

公开(公告)日：2010-03-24

申请号：EP04702490

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7836 ,  Y10S257/90