公开(公告)号：DE112005000219T5

公开(公告)日：2006-12-07

申请号：DE112005000219

申请日：2005-01-10

Applicant: INTEL CORP

Inventor： BOGIN ZOHAR ,  HUNTER JR ,  VENKATARAMANA KRISHNAMURTHY

IPC: G06F13/16

Abstract: A method and apparatus for managing memory access requests have been disclosed. One embodiment of the method includes dynamically modifying attributes of each of a number of requests to access one or more memory devices and arbitrating among the requests to select a request to send to the memory devices in a time slot based on the attributes. Other embodiments are described and claimed.

公开(公告)号：SG11202107290QA

公开(公告)日：2021-09-29

申请号：SG11202107290Q

申请日：2020-03-14

Applicant: INTEL CORP

Inventor： RAY JOYDEEP ,  JANUS SCOTT ,  GEORGE VARGHESE ,  MAIYURAN SUBRAMANIAM ,  KOKER ALTUG ,  APPU ABHISHEK ,  SURTI PRASOONKUMAR ,  RANGANATHAN VASANTH ,  ANDREI VALENTIN ,  GARG ASHUTOSH ,  HAREL YOAV ,  HUNTER JR ,  KIM SUNGYE ,  MACPHERSON MIKE ,  OULD-AHMED-VALL ELMOUSTAPHA ,  SADLER WILLIAM ,  STRIRAMASSARMA LAKSHMINARAYANAN ,  VEMULAPALLI VIKRANTH

IPC: G06F9/30 ,  G06F9/38

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.