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    Primitives to enhance thread-level speculation
    2.
    发明专利
    Primitives to enhance thread-level speculation 未知

    公开(公告)号：GB2441665A

    公开(公告)日：2008-03-12

    申请号：GB0721281

    申请日：2006-06-23

    Applicant: INTEL CORP

    Inventor： JACOBSON QUINN A ,  WANG HONG ,  SHEN JOHN ,  CHINYA GAUTHAM ,  ZOU XIANG ,  BIGBEE BRYANT ,  KAUSHKI SHIVNANDAN ,  HAMMERLUND PER

    IPC: G06F9/38 ,  G06F9/46

    Abstract: A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

    Suspending other threads to prevent access conflicts
    8.
    发明专利
    Suspending other threads to prevent access conflicts 未知

    公开(公告)号：GB2457181A

    公开(公告)日：2009-08-12

    申请号：GB0907512

    申请日：2006-06-23

    Applicant: INTEL CORP

    Inventor： JACOBSON QUINN A ,  WANG HONG ,  SHEN JOHN ,  CHINYA GAUTHAM ,  HAMMERLUND PER ,  ZOU XIANG ,  BIGBEE BRYANT ,  KAUSHKI SHIVNANDAN

    IPC: G06F9/46 ,  G06F9/38

    Abstract: Threads are executed concurrently in a computer system. They may be executed on separate processors or on a single processor with hardware support for simultaneous multithreading (SMT). The threads share a common view of the memory of the system. In order to allow a block of instructions to execute atomically, all but one of the threads are suspended. The threads may be suspended by writing a predefined value to a specified memory location. This may cause an interrupt, which suspends the threads. The threads may be suspended in response to a user level instruction. The processor may include hardware to support transactional memory, such as a buffer to store write data and an area to store read addresses.

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