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    A METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
    1.
    发明专利
    A METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 未知

    公开(公告)号：MY151464A

    公开(公告)日：2014-05-30

    申请号：MYUI2010005859

    申请日：2010-12-09

    Applicant: MIMOS BERHAD

    Inventor： WAH LEE HING ,  SHENG DANIEL BIEN CHIA ,  SYONO MOHD ISMAHADI ,  RANI ROZINA ABDUL

    IPC: H01L21/20

    Abstract: THE PRESENT INVENTION RELATES TO A METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE USING A LIFT-OFF METHOD. THE METHOD COMPRISES THE STEPS OF DEPOSITING AND PATTERNING A SACRIFICIAL LAYER (22) ONTO A SUBSTRATE (21), WHEREIN AT LEAST ONE PORTION OF THE SUBSTRATE SURFACE (21A) IS COVERED BY THE SACRIFICIAL LAYER (22) AND AT LEAST ONE PORTION OF THE SUBSTRATE SURFACE (21B) IS EXPOSED; DEPOSITING AND PATTERNING A CHEMICAL RESIST (23) ONTO THE SACRIFICIAL LAYER (22) AND THE EXPOSED SUBSTRATE SURFACE (21 B); REMOVING THE SACRIFICIAL LAYER (22); DEPOSITING A SEMICONDUCTOR FILM (24) ONTO THE SUBSTRATE (21) AND THE CHEMICAL RESIST (23); AND REMOVING THE CHEMICAL RESIST (23) AND THE SEMICONDUCTOR FILM (24) DEPOSITED ON THE CHEMICAL RESIST (23).

    FABRICATION METHOD OF A MICROMECHANICAL DEVICE
    2.
    发明专利
    FABRICATION METHOD OF A MICROMECHANICAL DEVICE 未知

    公开(公告)号：MY143881A

    公开(公告)日：2011-07-15

    申请号：MYPI20071932

    申请日：2007-11-07

    Applicant: MIMOS BERHAD

    Inventor： BUYONG MUHAMAD RAMDZAN ,  ZAIN AZLINA MOHD ,  MOHAMAD SITI AISHAH ,  SYONO MOHD ISMAHADI ,  WAH LEE HING ,  KASJOO SHAHRIR RIZAL

    IPC: B81C1/00

    Abstract: FABRICATION METHOD OF A MICROMECHANICAL DEVICE 5 A METHOD FOR FABRICATING A MICROMECHANICAL DEVICE COMPRISES THE STEPS OF PROVIDING A SUBSTRATE HAVING A FIRST DIELECTRIC LAYER ON TOP SURFACE OF SAID SUBSTRATE, A BOTTOM CONDUCTIVE LAYER ON TOP SURFACE OF SAID FIRST DIELECTRIC LAYER, A SECOND DIELECTRIC LAYER ON SAID BOTTOM CONDUCTIVE LAYER, A 0 SACRIFICIAL LAYER ON SAID SECOND DIELECTRIC LAYER, A THIRD DIELECTRIC LAYER ON SAID SACRIFICIAL LAYER, AND A TOP CONDUCTIVE LAYER ON SAID THIRD DIELECTRIC LAYER, ETCHING A PLURALITY OF HOLES AT SAID TOP CONDUCTIVE LAYER, THEN AT SAID THIRD DIELECTRIC LAYER AND SAID SACRIFICIAL LAYER, AND SEALING 5 SAID ETCHED HOLES OF SAID TOP CONDUCTIVE LAYER AND THIRD DIELECTRIC LAYER BY DEPOSITING A FOURTH DIELECTRIC LAYER ON TOP OF SAID TOP CONDUCTIVE LAYER. MOST ILLUSTRATIVE DIAGRAM:

    A REFERENCE ELECTRODE AND A METHOD THEREOF
    4.
    发明专利
    A REFERENCE ELECTRODE AND A METHOD THEREOF 未知

    公开(公告)号：MY145241A

    公开(公告)日：2012-01-10

    申请号：MYPI20094067

    申请日：2009-09-29

    Applicant: MIMOS BERHAD

    Inventor： SYONO MOHD ISMAHADI ,  RANI ROZINA ABDUL

    IPC: G01N27/414

    Abstract: A REFERENCE ELECTRODE (130) FOR SENSING PH IS PROVIDED IN AN AMBIENT ELECTROLYTE SOLUTION IN AN ION SENSITIVE FIELD EFFECT TRANSISTOR (ISFET) (100) WHICH INCLUDES A SOURCE (160), A DRAIN (150) AND A GATE (140), CHARACTERIZED IN THAT, THE REFERENCE ELECTRODE (130) INCLUDES AN ALTERNATING CURRENT SOURCE, AN INSULATING MEMBRANE SEPARATING THE REFERENCE ELECTRODE (130) FROM THE AMBIENT ELECTROLYTE SOLUTION, A DIRECT CURRENT (DC) BIASING VOLTAGE (170) AT THE GATE (140) WHEREIN THE VOLTAGE IS A PREDETERMINED CONSTANT VOLTAGE, WHEREIN THE REFERENCE ELECTRODE (130) IS CONNECTABLE TO THE ALTERNATING CURRENT SOURCE (120) WHERE THE REFERENCE ELECTRODE (130) IS FURTHER INCLUDED IN THE GATE (140) AND THE REFERENCE ELECTRODE (130) IS CONSTRUCTED FROM COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) COMPATIBLE METAL.

    MEMS BASED PROBE CARD AND A METHOD OF TESTING SEMICONDUCTOR ION SENSOR USING THE SAME
    6.
    发明专利
    MEMS BASED PROBE CARD AND A METHOD OF TESTING SEMICONDUCTOR ION SENSOR USING THE SAME 未知

    公开(公告)号：MY144280A

    公开(公告)日：2011-08-29

    申请号：MYPI20072045

    申请日：2007-11-20

    Applicant: MIMOS BERHAD

    Inventor： SYONO MOHD ISMAHADI

    Abstract: NIEMS BASED PROBE CARD AND A METHOD OF TESTING SEMICONDUCTOR ION SENSOR USING THE SAME ABSTRACT AN MEMS BASED PROBE CARD (I 00) FOR TESTING INTEGRATED CIRCUITS AT WAFER LEVEL 5 COMPRISING A PRINTED CIRCUIT BOARD (1) IN WHICH AN OPENING IS FORMED ON A MIDDLE PORTION THERETHROUGH; AT LEAST TWO OPPOSING FIRST ELECTRODE PAD (3) BEING DEPOSITED ON A PERIPHERY OF THE PRINTED CIRCUIT BOARD (1); AND A WAFER ASSEMBLY DISPOSED AROUND THE CENTRAL OF THE PRINTED CIRCUIT BOARD (1) COMPRISING A SUBSTRATE LAYER (5) IN WHICH AN OPENING IS FORMED ON A MIDDLE PORTION THERETHROUGH;AN INSULATING LAYER (7) ON THE I 0 SUBSTRATE LAYER (5); AT LEAST TWO OPPOSING SECOND ELECTRODE PADS (9) IN THE PERIPHERAL REGION OF THE INSULATING LAYER (7); AND A PROBE PIN (I 1) ON EACH SECOND ELECTRODE PAD (9), WHEREIN THE FIRST ELECTRODE PADS (3) ARID THE SECOND ELECTRODE PADS (9) ARE ELECTRICALLY INTERCONNECTED BY A ELECTRICAL CONDUCTOR (I 3). THE MOST ILLUSTRATIVE DRAWING:

    METHOD OF FABRICATING INTEGRATED REFERENCE ELECTRODE
    10.
    发明专利
    METHOD OF FABRICATING INTEGRATED REFERENCE ELECTRODE 未知

    公开(公告)号：MY150721A

    公开(公告)日：2014-02-28

    申请号：MYPI20097021

    申请日：2009-10-24

    Applicant: MIMOS BERHAD

    Inventor： WAH LEE HING ,  SYONO MOHD ISMAHADI

    IPC: G01N27/30

    Abstract: THE PROPOSED INVENTION PROPOSES AN IMPROVED METHOD OF FABRICATING REFERENCE ELECTRODE. PART OF THE REFERENCE ELECTRODE IS FABRICATED, COMPRISING: PATTERNING AND ETCHING A FIRST SIDE OF A GLASS WAFER (20) TO CREATE A PAIR OF CAVITIES (22); CHARACTERIZED IN THAT; PATTERNING AND ETCHING A SIDE OF GLASS WAFER TO CREATE A CHANNEL (24) TO LINK THE CAVITIES; AND DEPOSITING A LAYER OF GLASS FRIT (26) ON THE SECOND SIDE OF THE GLASS WAFER. THE NOVELTY OF THE INVENTION LAYS IN THE CHANNEL (24) BETWEEN TWO CAVITIES AND A LAYER OF GRASS FRIT (26) THE CAVITIES. THE GLASS FRIT USED IS PREFERABLY A RELATIVELY HIGH POROSITY GLASS FRIT. HENCE, AN INTEGRATED REFERENCE ELECTRODE IS CHARACTERIZED IN THAT; THE WAFER IS SHAPED TO FORM A CHANNEL (24) THAT CONNECTS BOTH CAVITIES AND A MEMBRANE OF GLASS FRIT (26A) IS PLACED BETWEEN THE TEST SOLUTION CAVITY AND THE CHANNEL.

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