公开(公告)号：JP2007103936A

公开(公告)日：2007-04-19

申请号：JP2006267781

申请日：2006-09-29

Applicant: Osram Opto Semiconductors Gmbh ,  オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングOsram Opto Semiconductors GmbH

Inventor： PLOESL ANDREAS ,  KRAEUTER GERTRUD ,  BUTENDEICH RAINER

IPC: H01L33/00 ,  H01L33/04 ,  H01L33/12 ,  H01S5/32

CPC classification number: H01L33/12 ,  H01L21/02395 ,  H01L21/02439 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/02664 ,  H01L33/0062 ,  H01L33/04 ,  H01S5/0217

Abstract: PROBLEM TO BE SOLVED: To provide an epitaxial substrate that achieves a peeling technology even in a arseniuretted-gallium-based material, has a sacrifice layer deposited on a wafer substrate, and has a group III-V semiconductor. SOLUTION: The epitaxial substrate has the sacrifice layer deposited on the wafer substrate, and the group III-V semiconductor. In this case, the band gap of the sacrifice layer is smaller than that of a peripheral substrate. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了提供即使在砷化镓基材料中实现剥离技术的外延基板，在晶片衬底上沉积有牺牲层，并且具有III-V族半导体。 解决方案：外延衬底具有沉积在晶片衬底上的牺牲层和III-V族半导体。 在这种情况下，牺牲层的带隙比外围基板的带隙小。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007103932A

公开(公告)日：2007-04-19

申请号：JP2006263255

申请日：2006-09-27

Applicant: Osram Opto Semiconductors Gmbh ,  オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングOsram Opto Semiconductors GmbH

Inventor： PLOESL ANDREAS

IPC: H01L33/00 ,  H01S5/323

CPC classification number: C30B29/403 ,  C30B25/18 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02546 ,  H01L21/76251 ,  H01L33/0079

Abstract: PROBLEM TO BE SOLVED: To provide a means capable of separating a substrate even if the substrate is formed of the other material system. SOLUTION: At least one layer contains a group III-V porous semiconductor material. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：即使基板由其他材料系统形成，也提供能够分离基板的装置。 解决方案：至少一层包含III-V族多孔半导体材料。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：DE102004016697B4

公开(公告)日：2007-10-11

申请号：DE102004016697

申请日：2004-04-05

Applicant: OSRAM OPTO SEMICONDUCTORS GMBH

Inventor： PLOESL ANDREAS

IPC: H01L21/301 ,  H01L21/58 ,  H01L33/00 ,  H01L33/62 ,  H01S5/022

公开(公告)号：DE102005047152A1

公开(公告)日：2007-04-12

申请号：DE102005047152

申请日：2005-09-30

Applicant: OSRAM OPTO SEMICONDUCTORS GMBH

Inventor： PLOESL ANDREAS ,  KRAEUTER GERTRUD ,  BUTENDEICH RAINER

IPC: H01L33/00 ,  H01L33/04 ,  H01L33/12

Abstract: The substrate has a sacrificial layer (32) attached on a wafer substrate, where a band gap of the sacrificial layer is smaller than a band gap of a gallium arsenide. An epitaxial layer (33) has a band gap that is larger than the band gap of the sacrificial layer. The sacrificial layer contains germanium, gallium arsenide nitride, gallium arsenide antimonide and indium gallium arsenide. The sacrificial layer has a super lattice structure, which is arranged at a lattice structure of wafers. A lattice adjustment layer (35b) is located between the sacrificial layer and epitaxial layer. Independent claims are also included for the following: (1) an LED-thin film chip, which is manufactured by an epitaxial substrate; (2) a method for manufacturing an epitaxial substrate; and (3) a method for manufacturing a light emitting diode thin film chip.

公开(公告)号：DE10307280A1

公开(公告)日：2004-06-17

申请号：DE10307280

申请日：2003-02-20

Applicant: OSRAM OPTO SEMICONDUCTORS GMBH

Inventor： ILLEK STEFAN ,  PLOESL ANDREAS

IPC: H01L33/24 ,  H01L33/30 ,  H01L33/40 ,  H01L33/00

Abstract: The production of a light-emitting semiconductor component comprises forming a layer sequence (14) consisting of an active zone (17) emitting photons on a substrate, applying an insulating layer (24) on the layer sequence and forming one or more through-contacts (28) in the insulating layer, applying a reflection contact layer (40) on the insulating layer, applying a diffusion barrier layer (42) on the reflection contact layer, applying and structuring a solder contact layer (44) on the barrier layer, and cleaning the layer sequence with an etching solution.. The contact layer is tempered after applying the insulating layer and before applying the barrier layer to form an ohmic contact. The surface of the contact layer is purified with an etching solution after tempering. An Independent claim is also included for an alternative process for the production of a light-emitting semiconductor component.

公开(公告)号：DE10243757A1

公开(公告)日：2004-04-01

申请号：DE10243757

申请日：2002-09-20

Applicant: OSRAM OPTO SEMICONDUCTORS GMBH

Inventor： KAISER STEPHAN ,  HAERLE VOLKER ,  PLOESL ANDREAS ,  HAHN BERTHOLD

IPC: C30B33/00 ,  H01L21/20 ,  H01L21/268 ,  H01L21/762 ,  H01L21/78 ,  H01L33/00 ,  H01L21/58

Abstract: A semiconductor layer grown on a substrate is applied to a carrier and separated from the substrate by irradiating with a pulsed laser beam. The thermal expansion coefficient of the carrier is matched to the radiation profile and pulse length of the laser beam pulse, and to the thermal expansion coefficient of the semiconductor layer and the thermal expansion coefficient of the substrate, to reduce strain between the substrate, semiconductor layer and carrier during manufacture. The semiconductor layer contains a nitride compound semiconductor. The carrier includes an iron-nickel-cobalt alloy. The substrate includes silicon, silicon carbide or aluminum oxide, especially sapphire.

公开(公告)号：DE10112542A1

公开(公告)日：2002-10-02

申请号：DE10112542

申请日：2001-03-15

Applicant: OSRAM OPTO SEMICONDUCTORS GMBH

Inventor： KRAEUTER GERTRUD ,  PLOESL ANDREAS ,  JACOB ULRICH

IPC: H01L33/32 ,  H01L33/42 ,  H01L33/46 ,  H01L33/54 ,  H01L33/00 ,  H01S5/026

Abstract: The invention relates to a radiation-emitting semiconductor component comprising a layered structure (30) containing an active layer (32) which, when in operation, emits radiation of a spectral distribution (60), and electrical contacts (36,38,40) for impressing a current in the layered structure (30). Said component comprises an anti-reflection coating (44) which at least partially surrounds the active layer (32) and retains a short-wave part of the emitted radiation (60).

公开(公告)号：DE102012215067A1

公开(公告)日：2014-02-27

申请号：DE102012215067

申请日：2012-08-24

Applicant: OSRAM OPTO SEMICONDUCTORS GMBH

Inventor： PLOESL ANDREAS ,  ZULL HERIBERT

IPC: H01L21/301 ,  H01L21/306 ,  H01L21/308 ,  H01L31/18 ,  H01L33/00

Abstract: Die Erfindung betrifft ein Verfahren zum Herstellen von vereinzelten Halbleiterbauelementen (191, 192). Das Verfahren umfasst ein Bereitstellen eines Ausgangssubstrats (100), und ein Durchführen eines Ätzprozesses zum Ausbilden von Vertiefungen (160) an einer Seite (102) des Ausgangssubstrats (100). Die Vertiefungen (160) sind im Bereich der herzustellenden Halbleiterbauelemente (191, 192) angeordnet. Zwischen den Vertiefungen (160) vorliegende Wandungen (161) sind im Bereich von zum Durchtrennen des Ausgangssubstrats (100) vorgesehenen Trennbereichen (140) angeordnet. Das Verfahren umfasst des Weiteren ein Ausbilden einer metallischen Schicht (130) auf der Seite (102) des Ausgangssubstrats (100) mit den Vertiefungen (160) und Wandungen (161), und ein Durchführen eines weiteren Ätzprozesses zum Durchtrennen des Ausgangssubstrats (100) in den Trennbereichen (140) und Bilden der vereinzelten Halbleiterbauelemente (191, 192).

公开(公告)号：DE102010003112A1

公开(公告)日：2011-09-22

申请号：DE102010003112

申请日：2010-03-22

Applicant: OSRAM OPTO SEMICONDUCTORS GMBH

Inventor： PERZLMAIER KORBINIAN ,  PLOESL ANDREAS

IPC: H01L21/66 ,  G01N21/95

Abstract: Verschiedene Ausführungsformen des Verfahrens zur Kontrolle einer zwischen einer Metallschicht (102) und einer Halbleiterschicht (100) ausgebildeten Grenzfläche (106) weisen die folgenden Schritte auf: – Die Grenzfläche (106) wird mit Infrarotstrahlung (302) bestrahlt. – Eine an der Grenzfläche (106) reflektierte Strahlung (304) wird erfasst. – Ein erfasstes Reflexionsbild wird mit einem erwarteten Reflexionsbild verglichen.

公开(公告)号：DE102008050573A1

公开(公告)日：2010-04-08

申请号：DE102008050573

申请日：2008-10-06

Applicant: OSRAM OPTO SEMICONDUCTORS GMBH

Inventor： PLOESL ANDREAS

IPC: H01L33/00

Abstract: An optoelectronic semiconductor component includes a semiconductor body connected to a main area of a carrier body by a solder layer, wherein sidewalls of the semiconductor body are provided with a dielectric layer, and a mirror layer applied to the dielectric layer.