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公开(公告)号：SG11202004020TA
公开(公告)日：2020-07-29
申请号：SG11202004020T
申请日：2018-12-10
Applicant: QUALCOMM INC
Inventor： KIM DANIEL DAEIK , KOO BONHOON , NEJATI BABAK
Abstract: A vertical inductor structure includes a first laminate substrate forming a first portion of the vertical inductor structure and a second laminate substrate forming a second portion. Each laminate substrate includes a plurality of first traces embedded in a layer of the laminate substrate, a plurality of first vertical columns, and a plurality of second vertical columns. Each first vertical columns is coupled to a first end of a respective first trace, and each second vertical column is coupled to a second end of a respective first trace. The second laminate substrate is mounted on the first laminate substrate such that each first vertical column of the first laminate substrate is coupled to a respective first vertical column of the second laminate substrate, and each second vertical column of the first laminate substrate is coupled to a respective second vertical column of the second laminate substrate.
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公开(公告)号：BR112015020828B1
公开(公告)日：2022-02-08
申请号：BR112015020828
申请日：2014-02-21
Applicant: QUALCOMM INC
Inventor： HADJICHRISTOS ARISTOTELE , NEJATI BABAK , RYAN D LANE , CHEN XIAOMING , ZHANG XIAONAN , YOUNG K SONG , PARK YUNSEO
IPC: H01L23/64 , H01L23/522 , H01L25/065 , H01L25/07 , H01L25/11
Abstract: indutor de fator de alta qualidade implementado em empacotamento de nível de wafer (wlp). algumas características de novidade pertencem a um primeiro exemplo que fornece um dispositivo semicondutor que inclui um painel de circuito impresso (pcb), esferas de solda e uma matriz. o pcb inclui uma primeira camada metálica. o conjunto de esferas de solda é acoplado ao pcb. a matriz é acoplada a uma segunda camada metálica e a uma terceira camada metálica. a primeira camada metálica do pcb, o conjunto de esferas de solda, as segunda e terceira camadas metálicas da matriz são configurados para operar como um indutor no dispositivo semicondutor. em algumas implementações, a matriz inclui adicionalmente uma camada de passivação. a camada de passivação é posicionada entre a segunda camada metálica e a terceira camada metálica. em algumas implementações, a segunda camada metálica é posicionada entre a camada de passivação e o conjunto de esferas de solda.
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公开(公告)号：ES2864881T3
公开(公告)日：2021-10-14
申请号：ES14709823
申请日：2014-02-21
Applicant: QUALCOMM INC
Inventor： SONG YOUNG , PARK YUNSEO , ZHANG XIAONAN , LANE RYAN , NEJATI BABAK , HADJICHRISTOS ARISTOTELE , CHEN XIAOMING
IPC: H01L23/64 , H01L23/00 , H01L23/522 , H01L25/065 , H01L25/07 , H01L25/11
Abstract: Un dispositivo semiconductor que comprende: una placa de circuito impreso, PCB (202) que comprende una primera capa metálica (202a, 310); un conjunto de bolas de soldadura (204, 308) acopladas a la PCB; y Un chip (200) acoplado a la PCB a través del conjunto de bolas de soldadura (204, 308), comprendiendo el chip una segunda capa metálica (218, 304) y una tercera capa metálica (210, 302) y un conjunto de vías (212, 306) que acoplan la segunda capa metálica (218) y la tercera capa metálica (210, 302); en el que la primera capa metálica (202a, 310) de la PCB, el conjunto de bolas de soldadura (204, 308), las segunda y tercera capas metálicas (218; 210, 302) y el conjunto de vías (212, 306) del chip están configurados para funcionar como un inductor en el dispositivo; en el que la primera capa metálica (202a, 310) de la PCB, el conjunto de bolas de soldadura (204, 308), la segunda y tercera capas metálicas (218; 210, 302) y el conjunto de vías (212, 306) del chip están configurados para proporcionar un devanado para el inductor, teniendo el devanado un número de N vueltas que es 2 o más.
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公开(公告)号：SG11202007285UA
公开(公告)日：2020-08-28
申请号：SG11202007285U
申请日：2019-02-04
Applicant: QUALCOMM INC
Inventor： ZHANG SHU , KIM DANIEL DAEIK , GAN CHENQIAN , KOO BONHOON , NEJATI BABAK
Abstract: Some features pertain to a substrate, and a first inductor integrated into the substrate. The first inductor includes a plurality of first inductor windings in a first metal layer and a second metal layer. A second inductor is integrated into the substrate. The second inductor includes a first spiral in a third metal layer. The first spiral is located at least partially inside the plurality of first inductor windings, wherein the second inductor is perpendicular to the first inductor.
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公开(公告)号：IN4414CHN2014A
公开(公告)日：2015-09-04
申请号：IN4414CHN2014
申请日：2014-06-13
Applicant: QUALCOMM INC
Inventor： CABANILLAS JOSE , PRESTI CALOGERO D , NEJATI BABAK , KLEMENS GUY
IPC: H03H7/40
Abstract: An impedance matching circuit with at least one tunable notch filter for a power amplifier is disclosed. The power amplifier amplifies an input radio frequency (RF) signal and provides an amplified RF signal. The impedance matching circuit performs output impedance matching for the power amplifier and includes at least one tunable notch filter. Each tunable notch filter has a notch that can be varied in frequency to provide better attenuation of an undesired signal. The at least one tunable notch filter attenuates at least one undesired signal in the amplified RF signal. The at least one tunable notch filter may include (i) a first tunable notch filter to attenuate a first undesired signal at a second harmonic of the amplified RF signal and/or (ii) a second tunable notch filter to attenuate a second undesired signal at a third harmonic of the amplified RF signal.
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Patent Agency Ranking
公开(公告)号：IN2253CHN2014A
公开(公告)日：2015-06-12
申请号：IN2253CHN2014
申请日：2014-03-25
Applicant: QUALCOMM INC
Inventor： ASURI BHUSHAN SHANTI , NEJATI BABAK
Abstract: A wireless device with power combining power amplifiers to support transmission on multiple antennas is disclosed. The power amplifiers may be operated together to obtain higher output power or separately to support transmission on multiple antennas. In an exemplary design an apparatus includes first and second power amplifiers. The first power amplifier amplifies a first input signal and provides a first output signal for a first antenna in a first operating mode (e.g. a MIMO mode or a transmit diversity mode). The second power amplifier amplifies the first input signal or a second input signal and provides a second output signal for a second antenna in the first operating mode. The first and second power amplifiers are power combined in a second operating mode to provide a third output signal which has a higher maximum output power than the first or second output signal.
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公开(公告)号：ES2393256T3
公开(公告)日：2012-12-19
申请号：ES09760442
申请日：2009-11-25
Applicant: QUALCOMM INC
Inventor： ANIRUDDHAN SANKARAN , NARATHONG CHIEWCHARN , SRIDHARA RAVI , NEJATI BABAK
Abstract: Un procedimiento para convertir en sentido ascendente una señal de banda base que comprende:en un modo lineal, mezclar una señal de banda base en fase (BB I) con una señal de oscilador local en fase(LO I) usando un mezclador primario;en el modo lineal, mezclar una señal de banda base en cuadratura (BB Q) con una señal de oscilador localen cuadratura (LO Q) usando un mezclador secundario;en el modo lineal, combinar las salidas de los mezcladores primario y secundario para generar una señalconvertida en sentido ascendente; yen un modo polar, mezclar una señal de banda base de amplitud (BB) con una señal de oscilador localmodulada en fase (LO) usando el mezclador primario.
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公开(公告)号：WO2011022549A3
公开(公告)日：2011-04-21
申请号：PCT/US2010046021
申请日：2010-08-19
Applicant: QUALCOMM INC , ZHAO YU , NEJATI BABAK , PLETCHER NATHAN M , HADJICHRISTOS ARISTOTELE
Inventor： ZHAO YU , NEJATI BABAK , PLETCHER NATHAN M , HADJICHRISTOS ARISTOTELE
CPC classification number: H03F1/42 , H03F1/223 , H03F3/193 , H03F2200/318 , H03H7/40
Abstract: A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus includes a first active circuit (e.g., a driver amplifier), a second active circuit (e.g., a power amplifier), and a tunable inter-stage matching circuit coupled between the first and second active circuits. The tunable inter-stage matching circuit includes a tunable capacitor that can be varied in discrete steps to adjust impedance matching between the first and second active circuits. In an exemplary design, the tunable capacitor includes (i) a plurality of capacitors coupled in parallel and (ii) a plurality of switches coupled to the plurality of capacitors, one switch for each capacitor. Each switch may be turned on to select an associated capacitor or turned off to unselect the associated capacitor. The tunable capacitor may further include a fixed capacitor coupled in parallel with the plurality of capacitors.
Abstract translation: 描述了可以提高性能的可调谐级间匹配电路。 在示例性设计中，装置包括耦合在第一和第二有源电路之间的第一有源电路（例如，驱动器放大器），第二有源电路（例如，功率放大器）和可调谐级间匹配电路。 可调谐级间匹配电路包括可以在离散步骤中变化的可调谐电容器，以调整第一和第二有源电路之间的阻抗匹配。 在示例性设计中，可调谐电容器包括（i）并联耦合的多个电容器和（ii）耦合到多个电容器的多个开关，用于每个电容器的一个开关。 每个开关可以被接通以选择一个相关联的电容器或关闭以取消选择相关联的电容器。 可调谐电容器还可以包括与多个电容器并联耦合的固定电容器。
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公开(公告)号：WO2010068504A3
公开(公告)日：2010-08-19
申请号：PCT/US2009065962
申请日：2009-11-25
Applicant: QUALCOMM INC , ANIRUDDHAN SANKARAN , NARATHONG CHIEWCHARN , SRIDHARA RAVI , NEJATI BABAK
Inventor： ANIRUDDHAN SANKARAN , NARATHONG CHIEWCHARN , SRIDHARA RAVI , NEJATI BABAK
CPC classification number: H03C5/00 , H03C3/40 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/1491 , H03D7/165 , H03D7/166 , H03D2200/0023 , H03D2200/0084 , H03G3/3042 , H04L27/34 , H04L27/36 , H04L27/361 , H04L27/362 , H04L27/38 , H04L27/389
Abstract: Method and apparatus for configuring a transmitter circuit to support linear or polar mode. In the linear mode, a baseband signal is specified by adjusting the amplitudes of in-phase (I) and quadrature (Q) signals, while in the polar mode, the information signal is specified by adjusting the phase of a local oscillator (LO) signal and the amplitude of either an I or a Q signal. In an exemplary embodiment, two mixers are provided for both linear and polar mode, with a set of switches selecting the appropriate input signals provided to one of the mixers based on whether the device is operating in linear or polar mode. In an exemplary embodiment, each mixer may be implemented using a scalable architecture that efficiently adjusts mixer size based on required transmit power.
Abstract translation: 用于配置发射机电路以支持线性或极性模式的方法和设备。 在线性模式中，通过调整同相（I）和正交（Q）信号的幅度来指定基带信号，而在极性模式中，通过调整本地振荡器（LO）的相位来指定信息信号， 信号和I或Q信号的幅度。 在示例性实施例中，为线性模式和极性模式提供两个混频器，其中一组开关基于设备是以线性还是极性模式工作来选择提供给混频器之一的适当输入信号。 在示例性实施例中，可以使用基于所需发射功率有效地调整混频器大小的可扩展架构来实现每个混频器。
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10.发明申请
公开(公告)号：WO2011008562A2
公开(公告)日：2011-01-20
申请号：PCT/US2010040488
申请日：2010-06-29
Applicant: QUALCOMM INC , KLEMENS GUY , MYERS THOMAS A , FREDERICK JR NORMAN L , ZHAO YU , NEJATI BABAK , PLETCHER NATHAN M , HADJICHRISTOS ARISTOTELE
Inventor： KLEMENS GUY , MYERS THOMAS A , FREDERICK JR NORMAN L , ZHAO YU , NEJATI BABAK , PLETCHER NATHAN M , HADJICHRISTOS ARISTOTELE
CPC classification number: H03F3/195 , H01L23/645 , H01L23/66 , H01L2223/6655 , H01L2223/6661 , H01L2224/16225 , H01L2924/00014 , H01L2924/1305 , H01L2924/19015 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
Abstract: A compact integrated power amplifier is described herein. In an exemplary design, an apparatus includes (i) an integrated circuit (IC) die having at least one transistor for a power amplifier and (ii) an IC package having a load inductor for the power amplifier. The IC die is mounted on the IC package with the transistor(s) located over the load inductor. In an exemplary design, the IC die includes a transistor manifold that is placed over the load inductor on the IC package. The transistor(s) are fabricated in the transistor manifold, have a drain connection in the center of the transistor manifold, and have source connections on two sides of the transistor manifold. The IC die and the IC package may include one or more additional power amplifiers. The transistor(s) for each power amplifier may be located over the load inductor for that power amplifier.
Abstract translation: 这里描述了紧凑的集成功率放大器。 在示例性设计中，装置包括（i）具有用于功率放大器的至少一个晶体管的集成电路（IC）管芯，以及（ii）具有用于功率放大器的负载电感器的IC封装。 IC芯片安装在IC封装上，晶体管位于负载感应器上方。 在示例性设计中，IC管芯包括放置在IC封装上的负载电感器上的晶体管歧管。 晶体管制造在晶体管歧管中，在晶体管歧管的中心具有漏极连接，并且在晶体管歧管的两侧具有源极连接。 IC芯片和IC封装可以包括一个或多个附加的功率放大器。 每个功率放大器的晶体管可以位于该功率放大器的负载电感上。
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