公开(公告)号：AU2003256826A8

公开(公告)日：2004-02-16

申请号：AU2003256826

申请日：2003-07-25

Applicant: QUALCOMM INC

Inventor： GREGORICH TOM ,  LANE RYAN ,  REYES EDWARD ,  VEATCH MARK

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065

公开(公告)号：ES2864881T3

公开(公告)日：2021-10-14

申请号：ES14709823

申请日：2014-02-21

Applicant: QUALCOMM INC

Inventor： SONG YOUNG ,  PARK YUNSEO ,  ZHANG XIAONAN ,  LANE RYAN ,  NEJATI BABAK ,  HADJICHRISTOS ARISTOTELE ,  CHEN XIAOMING

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/522 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11

Abstract: Un dispositivo semiconductor que comprende: una placa de circuito impreso, PCB (202) que comprende una primera capa metálica (202a, 310); un conjunto de bolas de soldadura (204, 308) acopladas a la PCB; y Un chip (200) acoplado a la PCB a través del conjunto de bolas de soldadura (204, 308), comprendiendo el chip una segunda capa metálica (218, 304) y una tercera capa metálica (210, 302) y un conjunto de vías (212, 306) que acoplan la segunda capa metálica (218) y la tercera capa metálica (210, 302); en el que la primera capa metálica (202a, 310) de la PCB, el conjunto de bolas de soldadura (204, 308), las segunda y tercera capas metálicas (218; 210, 302) y el conjunto de vías (212, 306) del chip están configurados para funcionar como un inductor en el dispositivo; en el que la primera capa metálica (202a, 310) de la PCB, el conjunto de bolas de soldadura (204, 308), la segunda y tercera capas metálicas (218; 210, 302) y el conjunto de vías (212, 306) del chip están configurados para proporcionar un devanado para el inductor, teniendo el devanado un número de N vueltas que es 2 o más.

公开(公告)号：MXPA06009583A

公开(公告)日：2007-03-26

申请号：MXPA06009583

申请日：2005-02-16

Applicant: QUALCOMM INC

Inventor： GAGNE JUSTIN ,  VEATCH MARK S ,  LANE RYAN

IPC: H01L23/50 ,  H01L23/498 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11

Abstract: Un dispositivo semiconductor de alta velocidad incluye un substrato que tiene una superficie de substrato superior, una superficie de substrato inferior, y una periferia que guia superficies de substrato superior e inferior, el substrato ademas tiene una traza a tierra de substrato superior que provee la trayectoria electrica a la superficie de substrato inferior a traves de una via a tierra de substrato; una disposicion de esferas de soldadura fijas a la superficie de substrato inferior, la disposicion de esferas de soldadura incluye una pluralidad de esferas de soldadura a tierra colocadas en la periferia y electricamente conectadas a la via a tierra del substrato.

公开(公告)号：AT417357T

公开(公告)日：2008-12-15

申请号：AT04707086

申请日：2004-01-30

Applicant: QUALCOMM INC

Inventor： REYES EDWARD ,  LANE RYAN ,  MARBURGER TIONA ,  GREGORICH TOM

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H05K3/34

Abstract: An area area package includes a plurality of solder balls not used as electrical connectors. These non-connected solder balls, or "dummy balls," provide protection to solder balls connected to live pins and therefore increase reliability of the area array package. The dummy balls may be placed in the corners, along the diagonals or in other high stress location on the area array package. To further increase reliability, a continuous copper ball land pad may be used to connect each group of corner dummy balls. Continuous copper pads help to reduce stress on the dummy balls. For center-depopulated BGA packages, an array of dummy balls may be used in the center of the package to prevent substrate bending and improve drop test reliability.

公开(公告)号：BR0312958A

公开(公告)日：2007-07-10

申请号：BR0312958

申请日：2003-07-25

Applicant: QUALCOMM INC

Inventor： LANE RYAN ,  REYES EDWARD ,  VEATCH MARK ,  GREGORICH TOM

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065

公开(公告)号：AU2003256826A1

公开(公告)日：2004-02-16

申请号：AU2003256826

申请日：2003-07-25

Applicant: QUALCOMM INC

Inventor： VEATCH MARK ,  GREGORICH TOM ,  LANE RYAN ,  REYES EDWARD

IPC: H01L23/498 ,  H01L23/00

公开(公告)号：DE602004018268D1

公开(公告)日：2009-01-22

申请号：DE602004018268

申请日：2004-01-30

Applicant: QUALCOMM INC

Inventor： REYES EDWARD ,  LANE RYAN ,  MARBURGER TIONA ,  GREGORICH TOM

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H05K3/34

Abstract: An area area package includes a plurality of solder balls not used as electrical connectors. These non-connected solder balls, or "dummy balls," provide protection to solder balls connected to live pins and therefore increase reliability of the area array package. The dummy balls may be placed in the corners, along the diagonals or in other high stress location on the area array package. To further increase reliability, a continuous copper ball land pad may be used to connect each group of corner dummy balls. Continuous copper pads help to reduce stress on the dummy balls. For center-depopulated BGA packages, an array of dummy balls may be used in the center of the package to prevent substrate bending and improve drop test reliability.

公开(公告)号：WO2004012262A3

公开(公告)日：2004-04-08

申请号：PCT/US0323405

申请日：2003-07-25

Applicant: QUALCOMM INC

Inventor： LANE RYAN ,  REYES EDWARD ,  VEATCH MARK ,  GREGORICH TOM

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An area array package comprising a die attach area for attaching a die to a substrate, a network of staggered bond fingers, and a network of bond islands for coupling bond wires between the bond islands and die bond pads is provided. A network of package leads, for example, a network of solder balls in a ball grid array, is depopulated to permit greater trace route flexibility and via placement within the substrate. Stacked die and multi-chip packages are also disclosed. A method for accommodating a high pin-count die in an area array package is also included

Abstract translation: 提供了一种面阵列封装，其包括用于将管芯附着到衬底的管芯附着区域，交错键合指状物的网络和用于耦合键合岛和管芯键合焊盘之间的键合引线的键合岛网络。 封装引线网络（例如球栅阵列中的焊球网络）被消减以允许更大的迹线路由灵活性并且通过放置在衬底内。 还公开了堆叠裸片和多芯片封装。 还包括在面阵列封装中容纳高引脚数芯片的方法

公开(公告)号：WO2004068560A2

公开(公告)日：2004-08-12

申请号：PCT/US2004002716

申请日：2004-01-30

Applicant: QUALCOMM INC ,  REYES EDWARD ,  LANE RYAN ,  MARBURGER TIONA ,  GREGORICH TOM

Inventor： REYES EDWARD ,  LANE RYAN ,  MARBURGER TIONA ,  GREGORICH TOM

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H05K3/34 ,  H01L

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2224/0401

Abstract: An area array package includes a plurality of solder balls not used as electrical connectors. These non-connected solder balls, or "dummy balls," provide protection to solder balls connected to live pins and therefore increase reliability of the area array package. The dummy balls may be placed in the corners, along the diagonals or in other high stress locations on the area array package. To further increase reliability, a continuous copper ball land pad may be used to connect each group of corner dummy balls. Continuous copper pads help to reduce stress on the dummy balls. For center-depopulated BGA packages, an array of dummy balls may be used in the center of the package to prevent substrate bending and improve drop test reliability.

Abstract translation: 面阵列封装包括多个不用作电连接器的焊球。 这些未连接的焊球或“虚拟球”为连接到带电引脚的焊球提供保护，并因此增加面阵列封装的可靠性。 虚拟球可以放置在面阵列封装的角落，对角线或其他高应力位置。 为了进一步提高可靠性，可以使用连续的铜球焊盘来连接每组角球模。 连续的铜垫有助于减少假球上的压力。 对于中心消失的BGA封装，可在封装中心使用一系列伪球，以防止衬底弯曲并提高跌落测试的可靠性。

公开(公告)号：WO2011063166A2

公开(公告)日：2011-05-26

申请号：PCT/US2010057305

申请日：2010-11-18

Applicant: QUALCOMM INC ,  RADOJCIC RATIBOR ,  CHANDRASEKARAN ARVIND ,  LANE RYAN

Inventor： RADOJCIC RATIBOR ,  CHANDRASEKARAN ARVIND ,  LANE RYAN

IPC: H01L23/52 ,  H01L21/60 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A hybrid interconnect includes a through silicon via and a wire bond. Hybrid interconnects enable better layout of a stacked IC by combining benefits from both interconnect technologies. In one hybrid interconnect, wire bonds couples a second tier die mounted on a first tier die to a redistribution layer in the first tier die. Through silicon vias in the first tier die are coupled to the wire bonds to provide communication. In another hybrid interconnect, a wire bond couples a redistribution layer on a first tier die to a packaging substrate on which the first tier die is mounted. The redistribution layer couples to a second tier die mounted on the first tier die to provide a power supply to the second tier die. Through silicon vias in the first tier die couple to the second tier die to provide communication from the packaging substrate to the second tier die.

Abstract translation: 混合互连包括硅通孔和引线键合。 混合互连通过结合两种互连技术的优势，实现更好的堆叠IC布局。 在一个混合互连中，引线接合将安装在第一层管芯上的第二层管芯耦合到第一层管芯中的重新分布层。 通过第一层裸片中的硅通孔耦合到引线键合以提供通信。 在另一种混合互连中，引线接合将第一层管芯上的重新分布层连接到其上安装第一层管芯的封装衬底。 再分布层耦合到安装在第一层管芯上的第二层管芯，以向第二层管芯提供电源。 通过第一层裸片中的硅通孔耦合到第二层裸片以提供从封装衬底到第二层裸片的通信。