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公开(公告)号：WO2021096717A8
公开(公告)日：2021-05-20
申请号：PCT/US2020/058536
申请日：2020-11-02
Applicant: RAYTHEON COMPANY
Inventor： SIKINA, Thomas, V. , HAVEN, John, P. , WILDER, Kevin , BENEDICT, James, E. , SOUTHWORTH, Andrew, R. , HERNDON, Mary, K.
IPC: H01Q21/06 , B33Y80/00 , H05K3/12 , H01Q1/52 , H01Q3/40 , H01Q1/241 , H01Q1/523 , H01Q1/528 , H01Q21/0087 , H01Q21/065 , H05K2201/10098 , H05K2201/10287 , H05K3/0044 , H05K3/043 , H05K3/4038
Abstract: A communications array includes a support structure configured to array elements, and a plurality of array elements supported by the support structure. Each array element is fabricated from an advanced manufacturing techniques (AMT) process. The support structure may be fabricated from a printed circuit board (RGB) or similar dielectric material. Each array element may include a radiator and/or a beamformer manufactured using the AMT process. The communications array further may include a copper vertical launch (CVL) and/or an electromagnetic boundary.
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公开(公告)号：WO2020251852A1
公开(公告)日：2020-12-17
申请号：PCT/US2020/036346
申请日：2020-06-05
Applicant: RAYTHEON COMPANY
Inventor： WILDER, Kevin , NUFIO-MOLINA, Jonathan, E. , THIESSEN, Phillip, W. , SIKINA, Thomas, V. , BENEDICT, James, E. , SOUTHWORTH, Andrew, R. , KLEK, Erika
Abstract: An array includes a support structure configured to support columns of beamformer assemblies, and a plurality of beamformer assemblies supported by the support structure. Each beamformer assembly includes at least one beamformer having at least one first beamformer segment and at least one second beamformer segment configured to interconnect with the first beamformer segment.
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公开(公告)号：WO2021096717A1
公开(公告)日：2021-05-20
申请号：PCT/US2020/058536
申请日：2020-11-02
Applicant: RAYTHEON COMPANY
Inventor： SIKINA, Thomas, V. , HAVEN, John, P. , WILDER, Kevin , BENEDICT, James, E. , SOUTHWORTH, Andrew, R. , HERNDON, Mary, K.
Abstract: A communications array includes a support structure configured to array elements, and a plurality of array elements supported by the support structure. Each array element is fabricated from an advanced manufacturing techniques (AMT) process. The support structure may be fabricated from a printed circuit board (RGB) or similar dielectric material. Each array element may include a radiator and/or a beamformer manufactured using the AMT process. The communications array further may include a copper vertical launch (CVL) and/or an electromagnetic boundary.
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公开(公告)号：WO2019094452A1
公开(公告)日：2019-05-16
申请号：PCT/US2018/059602
申请日：2018-11-07
Applicant: RAYTHEON COMPANY
Inventor： SIKINA, Thomas, V. , HAVEN, John, P. , BENEDICT, James, E. , NUFIO-MOLINA, Jonathan, E. , SOUTHWORTH, Andrew, R.
Abstract: A low profile array (LPA) includes an antenna element array layer having at least one Faraday wall, and a beamformer circuit layer coupled to the antenna element array layer. The beamformer circuit layer has at least one Faraday wall. The Faraday walls extends between ground planes associated with at least one of the antenna element array layer and the beamformer circuit layer.
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5.发明申请
公开(公告)号：WO2021252111A1
公开(公告)日：2021-12-16
申请号：PCT/US2021/031134
申请日：2021-05-06
Applicant: RAYTHEON COMPANY
Inventor： BENEDICT, James, E. , BENINATI, Gregory, G. , PEVZNER, Mikhail , SIKINA, Thomas, V. , SOUTHWORTH, Andrew, R.
IPC: H05K3/34 , H05K3/00 , H05K3/40 , H05K2201/0305 , H05K2201/09154 , H05K2201/09572 , H05K2203/041 , H05K2203/043 , H05K2203/046 , H05K3/0044 , H05K3/0047 , H05K3/3485 , H05K3/4038
Abstract: A process of fabricating a circuit includes providing a first sheet of dielectric material including a first top surface having at least one first conductive trace and a second sheet of dielectric material including a second top surface having at least one second conductive trace, depositing a first solder bump on the at least one first conductive trace, applying the second sheet of dielectric material to the first sheet of dielectric material with bonding film sandwiched in between, bonding the first and second sheets of dielectric material to one another, and providing a conductive material to connect the first solder bump on the at least one first conductive trace to the at least one second conductive trace.
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Patent Agency Ranking
公开(公告)号：WO2021055015A1
公开(公告)日：2021-03-25
申请号：PCT/US2020/026186
申请日：2020-04-01
Applicant: RAYTHEON COMPANY
Inventor： BENEDICT, James, E. , DELEY, Timothy, David , SIKINA, Thomas, V. , SOULIOTIS, Michael, Ryan , SOUTHWORTH, Andrew, R. , WILDER, Kevin
Abstract: A multilayer printed circuit board includes a first dielectric layer and a second dielectric layer, each layer having a top surface and a bottom surface. The first dielectric layer is positioned above the second dielectric layer with the bottom surface of the first dielectric layer facing the top surface of the second dielectric layer. The top surface of the second dielectric layer has a conductive trace. The second dielectric layer has a through-hole that extends through the conductive trace. The multilayer printed circuit board includes an inverted pad interface structure including an inverted pad provided on the bottom surface of the first dielectric layer, a first solder layer provided on a surface of the inverted pad, a second solder layer provided on the conductive trace, and a copper wire positioned within the through-hole to provide the vertical and electrical connection with the conductive trace.
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7.发明申请
公开(公告)号：WO2019094600A1
公开(公告)日：2019-05-16
申请号：PCT/US2018/059841
申请日：2018-11-08
Applicant: RAYTHEON COMPANY
Inventor： AZADZOI, Semira, M. , BENEDICT, James, E. , HAVEN, John, P. , SIKINA, Thomas, V. , SOUTHWORTH, Andrew, R.
CPC classification number: H05K1/0218 , H01P3/08 , H01P11/003 , H05K1/0219 , H05K1/0221 , H05K1/0251 , H05K1/112 , H05K3/0044 , H05K3/107 , H05K3/4007 , H05K3/4038 , H05K3/4611 , H05K2201/0707 , H05K2201/09036 , H05K2201/09545 , H05K2203/0228
Abstract: A radio frequency circuit includes at least one dielectric substrate, a trench formed in the dielectric substrate, and an electrically continuous conductive material in the trench. The radio frequency circuit further may include a first dielectric substrate, a second dielectric substrate, with the trench being formed in the first and second dielectric substrates. A method of fabricating an electromagnetic circuit includes providing at least one dielectric substrate, machining a trench in the at least one dielectric substrate, and filling the trench with an electrically conductive material to form an electrically continuous conductor.
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公开(公告)号：WO2021091825A1
公开(公告)日：2021-05-14
申请号：PCT/US2020/058540
申请日：2020-11-02
Applicant: RAYTHEON COMPANY
Inventor： PEVZNER, Mikhail , BENEDICT, James, E. , SOUTHWORTH, Andrew, R. , SCHWANDA, Wade, A.
Abstract: An apparatus to automatically place layers of a printed circuit board on a fixture includes a robotic device having a base that is secured to a surface, an upright column that extends upwardly from the base, and a movable arm rotatably coupled to the upright column. The movable arm is configured to rotate about a vertical axis defined by the upright column. The movable arm is further configured to rotate from a position in which the movable arm is disposed over a laminate sheet fixture and to pick up a laminate sheet to a position in which the movable arm is disposed over a board layup fixture to deposit the laminate sheet in the board layup fixture, and from a position in which the movable arm is disposed over a bond film fixture and to pick up a bond film to a position in which the movable arm is disposed over the board layup fixture to deposit the bond film in the board layup fixture.
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公开(公告)号：WO2019168996A1
公开(公告)日：2019-09-06
申请号：PCT/US2019/019851
申请日：2019-02-27
Applicant: RAYTHEON COMPANY
Inventor： NUFIO-MOLINA, Jonathan, E. , SIKINA, Thomas, V. , BENEDICT, James, E. , SOUTHWORTH, Andrew, R. , AZADZOI, Semira, M.
Abstract: A method of manufacturing a power divider circuit includes milling a conductive material disposed upon a first substrate to form a signal trace. The signal trace includes a division from a single trace to two arm traces, with each of the two arm traces having a proximal end electrically connected to the single trace and a distal end electrically connected to each of two secondary traces. The method further includes depositing a resistive ink between the two distal ends to form a resistive electrical connection between the two arm traces, bonding a second substrate to the first substrate to substantially encapsulate the traces between the first substrate and the second substrate, and milling through at least one of the first substrate or the second substrate to provide access to at least one of the traces. A signal divider is further disclosed.
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公开(公告)号：WO2019094470A1
公开(公告)日：2019-05-16
申请号：PCT/US2018/059625
申请日：2018-11-07
Applicant: RAYTHEON COMPANY
Inventor： SOUTHWORTH, Andrew, R. , SIKINA, Thomas, V. , HAVEN, John, P. , BENEDICT, James, E. , WILDER, Kevin
Abstract: Electromagnetic circuit structures and methods are provided for a circuit board that includes a hole disposed through a substrate to provide access to an electrical component, such as a signal trace line (or stripline), that is at least partially encapsulated (e.g., sandwiched) between substrates. The electrical component includes a portion substantially aligned with the hole, and an electrical conductor is disposed within the hole. The electrical conductor is soldered to the portion of the electrical component.
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