公开(公告)号：DE69519476D1

公开(公告)日：2000-12-28

申请号：DE69519476

申请日：1995-12-07

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： CAPOCELLI PIERO ,  ZAMBRANO RAFFAELE ,  PIO FEDERICO ,  RIVA CARLO

IPC: H01F17/00 ,  H01F41/04 ,  H01L23/522 ,  H01L27/04

Abstract: Inductive structures making highly efficient use of the magnetic flux generated, and being consistent with integrated circuit manufacturing techniques, and a method of making them on a semiconductor substrate concurrently with the formation of the integrated circuit itself.

公开(公告)号：DE69519476T2

公开(公告)日：2001-06-28

申请号：DE69519476

申请日：1995-12-07

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： CAPOCELLI PIERO ,  ZAMBRANO RAFFAELE ,  PIO FEDERICO ,  RIVA CARLO

IPC: H01F17/00 ,  H01F41/04 ,  H01L23/522 ,  H01L27/04

Abstract: Inductive structures making highly efficient use of the magnetic flux generated, and being consistent with integrated circuit manufacturing techniques, and a method of making them on a semiconductor substrate concurrently with the formation of the integrated circuit itself.

公开(公告)号：JPH08316346A

公开(公告)日：1996-11-29

申请号：JP19794395

申请日：1995-07-12

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FRATIN LORENZO ,  RAVAZZI LEONARDO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile memory including cells having an N type source region and a drain region surrounded by a P pocket buried in a P type substrate. SOLUTION: In order to improve a cell size and to avoid deterioration of a snap-back voltage, drain and source P pockets 16 and 26 are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage. Cells formed thereby exhibit a breakdown voltage higher than that of conventional cells.

公开(公告)号：JPH10270440A

公开(公告)日：1998-10-09

申请号：JP1849098

申请日：1998-01-30

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CALEGARI CAMILLA ,  CARRARA ANNA ,  FRATIN LORENZO ,  RIVA CARLO

IPC: H01L23/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To perfectly seal the ends of the device by forming recesses into first inner sections of a main surface of a planarized amorphous material layer- made morphologic structure within zones having continuous parts. SOLUTION: A mask 34 in a zone of a device end morphologic structure 30 is opened up to the ends of the device. A second polysilicon etching at an active region 8 located at the left of a field oxide film region 7 forms recesses R1 in a substrate 6. The recesses R1 locate in inner regions 3' of the structure 30 inside which a polymer circuit mask 35 having openings 36 is provided to form other recesses R2 at unmasked surface of Si, thus obtaining the recesses different in depth. This reduces the gradient of the steps between the recess bottom and Si surface 5.

公开(公告)号：JP2588058B2

公开(公告)日：1997-03-05

申请号：JP29219690

申请日：1990-10-31

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CAPPELLETTI PAOLO ,  CORDA GIUSEPPE ,  GHEZZI PAOLO ,  RIVA CARLO ,  VAJANA BRUNO

IPC: G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866

公开(公告)号：JPH03225875A

公开(公告)日：1991-10-04

申请号：JP29219690

申请日：1990-10-31

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CAPPELLETTI PAOLO ,  CORDA GIUSEPPE ,  GHEZZI PAOLO ,  RIVA CARLO ,  VAJANA BRUNO

IPC: G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866

Abstract: PURPOSE: To manufacture a component which controls and stabilizes a programming voltage by a method, wherein the N-channel and P-channel transistor of a corresponding control circuit device are formed in a following manufacturing process. CONSTITUTION: An N-type sink 2 is formed on a single-crystal silicon substrate 1, and an active region 14 is formed on the surface of the sink 2. An N -dopant 4 is implanted in the surface region of the sink 2 inside the active region 14, and a gate oxide layer 5 is grown on the N -dopant region. An N -region 6 is implanted inside the N -region 4, a P -region 7 is implanted at a position located sideways off the N -region 6, and an outer node 8 (13) is formed for the N and P -regions, 6 (9) and 7 (12). By this setup, a component for limiting a programming voltage and stabilizing it with a cut-off voltage which is temporarily stable and temperature-independent can be obtained.

公开(公告)号：DE69217846T2

公开(公告)日：1997-06-12

申请号：DE69217846

申请日：1992-10-30

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： GHEZZI PAOLO ,  PIO FEDERICO ,  RIVA CARLO

IPC: G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82

公开(公告)号：DE69030544D1

公开(公告)日：1997-05-28

申请号：DE69030544

申请日：1990-08-28

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： GHEZZI PAOLO ,  RIVA CARLO ,  VALENTINI GRAZIA

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

Abstract: The process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide with selection transistor (20), sensing transistor (22) having a floating gate (5), control gate (10) with a capacitive coupling to the floating gate (5) and a tunnel area (23) with thin oxide (9), comprises a first step (29) involving the definition of active areas (41, 42) free of field oxide (11), a second step (30) involving an ionic implantation (10 min ) at a coupling area (24) between the control gate (10) and the floating gate (5), a third step (31) involving the creation of gate oxide (21) at the active areas (41, 42), a fourth step (32) involving an additional ionic implantation (10 sec , 8) at said coupling area (24) between the control gate (10) and the floating gate (5) and at said tunnel area (23), a fifth step (33) involving the removal of the gate oxide (21) superimposed over said areas (24, 23), a sixth step (34) involving the differentiated growth of coupling oxide (12) and tunnel oxide (9) at said coupling areas (24) and tunnel areas (23) and a seventh step (35) involving the deposition of a layer of polysilicon (5) constituting the floating gate.

公开(公告)号：DE69305986D1

公开(公告)日：1996-12-19

申请号：DE69305986

申请日：1993-07-29

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PIO FEDERICO ,  RIVA CARLO ,  LUCHERINI SILVIA C O SGS-THOMS

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells (2) including plural rows (3) and columns (4), with each row (3) being provided with a word line (WL) and a control gate line (CG) and each column (4) having a bit line (BL); the bit lines (BL), moreover, are gathered into groups or bytes (9) of simultaneously addressable adjacent lines. Each cell (2) in the matrix incorporates a floating gate transistor (12) which is coupled to a control gate (8), connected to the control gate line (CG), and is connected serially to a selection transistor (5); also, the cells (2) of each individual byte (9) share their respective source areas (6), which areas are structurally independent for each byte (9) and are led to a corresponding source addressing line (SL) extending along a matrix column (7).

公开(公告)号：DE68922641T2

公开(公告)日：1996-02-08

申请号：DE68922641

申请日：1989-02-13

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： RIVA CARLO

IPC: H01L21/8247 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82