1.
    发明专利
    未知

    公开(公告)号:ITMI920344D0

    公开(公告)日:1992-02-18

    申请号:ITMI920344

    申请日:1992-02-18

    Abstract: The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.

    MONOLITHIC INTEGRATED CIRCUIT STRUCTURE WITH READ ONLY MEMORY CELL WHICH IS ELECTRICALLY PROGRAMMABLE

    公开(公告)号:JPH07254687A

    公开(公告)日:1995-10-03

    申请号:JP31187094

    申请日:1994-12-15

    Abstract: PURPOSE: To provide an integrated circuit structure, capable of forming a hybrid type integrated circuit having at least one EPROM without adding a special working step for the hybrid type integrated circuit regarding the integrated circuit. CONSTITUTION: An EPROM cell has an active region 18, and the region is formed by the same operation as the formation of a P-type region 17, in which an N -channel MOS transistor is housed. Likewise, each region of sources and drains is formed by the same operation as the formation of the source regions and drain regions 31 of the transistors, control electrodes 15 consisting of N - type regions are shaped by the same operation as the formation of deep regions 14 communicating each N -type embedded region, and floating gate electrodes 24 formed of one conductive material layer are formed by the same operation as the formation of the gate electrodes 23 of the transistors in an integrated circuit.

    10.
    发明专利
    未知

    公开(公告)号:IT8424126D0

    公开(公告)日:1984-12-18

    申请号:IT2412684

    申请日:1984-12-18

    Abstract: The disclosed bridge circuit is fabricated using power MOS technology. Common terminals of the bridge circuit are integrated into common regions in the implementation. Electrodes, typically coupled together in the bridge circuit, are implemented by a shared conducting region in the integrated circuit of the semiconductor chip. By integrating the elements of the circuit, less area of the semiconductor chip is required as compared to an implementation involving 4 (four) discrete elements. Diodes are fabricated across the transistors to protect the elements against reverse biasing.

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