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    MEMORY MODULE SYSTEM AND METHOD
    2.
    发明专利
    MEMORY MODULE SYSTEM AND METHOD 未知

    公开(公告)号：HK1121287A1

    公开(公告)日：2009-04-17

    申请号：HK09100449

    申请日：2009-01-16

    Applicant: STAKTEK GROUP LP

    Inventor： RAPPORT RUSSELL ,  GOODWIN PAUL ,  CADY JAMES W

    IPC: H01L20100101

    Abstract: A circuit module is provided in which two secondary substrates or cards or the rigid portions of a rigid flex assembly are populated with integrated circuits (ICs). The secondary substrates are connected with flexible circuitry. One side of the flexible circuitry exhibits contacts adapted for connection to an edge connector. The flexible circuitry is wrapped about an edge of a preferably metallic substrate to dispose one of the two secondary substrates on a first side of the substrate and the other of the secondary substrates on the second side of the substrate.

    MEMORY EXPANSION AND INTEGRATED CIRCUIT STACKING SYSTEM AND METHOD
    3.
    发明专利
    MEMORY EXPANSION AND INTEGRATED CIRCUIT STACKING SYSTEM AND METHOD 未知

    公开(公告)号：AU2003304192A1

    公开(公告)日：2005-01-04

    申请号：AU2003304192

    申请日：2003-09-15

    Applicant: STAKTEK GROUP LP

    Inventor： WEHRLY JAMES DOUGLAS JR ,  BUCHLE JEFF ,  RAPPORT RUSSELL ,  CADY JAMES W ,  WILDER JAMES ,  ROPER DAVID L

    IPC: H01L21/44 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the other. The two CSPs are connected with flex circuitry. A form standard is disposed between the flex circuitry and a CSP in the stack. The form standard can take many configurations and may be used where flex circuits are used to connect CSPs to one another in stacked modules having two or more constituent CSPs. For example, in stacked modules that include four CSPs, three form standards are employed in preferred embodiments, although fewer may be used. The form standard provides a thermally conductive physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.

    STACKED INTEGRATED CIRCUIT CASCADE SIGNALING SYSTEM AND METHOD
    4.
    发明申请
    STACKED INTEGRATED CIRCUIT CASCADE SIGNALING SYSTEM AND METHOD 审中-公开
    堆叠集成电路CASCADE信号系统和方法

    公开(公告)号：WO2006028693A3

    公开(公告)日：2009-09-03

    申请号：PCT/US2005029867

    申请日：2005-08-23

    Applicant: STAKTEK GROUP LP ,  CADY JAMES ,  RAPPORT RUSSELL ,  WILDER JAMES

    Inventor： CADY JAMES ,  RAPPORT RUSSELL ,  WILDER JAMES

    IPC: H01L23/02 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/48 ,  H01L21/50 ,  H01L23/04 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L25/105 ,  H01L23/4985 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: Integrated circuits (ICs) are stacked into modules that conserve PCB or other board surface area. The modules provide for lower capacitance memory signaling systems and methods for connecting stacked CSPs in a serial cascade arrangement. In one preferred embodiment, on-die terminations are used selectively to terminate a cascaded series of conductive paths. In another preferred embodiment, a form standard provides a physical form that allows many of the varying package sizes found in a broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.

    Abstract translation: 集成电路（IC）堆叠成可以节省PCB或其他板表面积的模块。 这些模块提供了较低电容存储器信号系统和用于以串联级联布置连接堆叠CSP的方法。 在一个优选实施例中，选择性地使用管芯端子来终止级联的导电路径。 在另一个优选实施例中，形式标准提供了一种物理形式，其允许在采用标准连接柔性电路设计的同时，在宽范围的CSP封装系列中发现许多变化的封装尺寸。

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