中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

43 records (took 0.03 seconds)

    Semiconductor device for electro-optic applications, method for manufacturing said device and corresponding semiconductor laser device
    1.
    发明公开
    Semiconductor device for electro-optic applications, method for manufacturing said device and corresponding semiconductor laser device 审中-公开
    Halftitervorrichtungfürelektro-optische Verwendung，Herstellungsverfahren und Halbleiterlaservorrichtung

    公开(公告)号：EP1081812A1

    公开(公告)日：2001-03-07

    申请号：EP99830544.5

    申请日：1999-09-02

    Applicant: STMicroelectronics S.r.l. ,  CNR-IMETEM

    Inventor： Coffa, Salvatore ,  Libertino, Sebania ,  Saggio, Mario ,  Frisina, Ferruccio

    IPC: H01S3/16 ,  H01S5/32

    CPC classification number: H01S5/305 ,  H01S3/1603 ,  H01S3/1628 ,  H01S5/3004 ,  H01S5/3068

    Abstract: The invention relates to a semiconductor device for electro-optic applications of the type including at least a rare-earth ions doped P/N junction integrated on a semiconductor substrate. This device may be used to obtain laser action in Silicon and comprises a cavity or a waveguide and a coherent light source obtained incorporating the rare-earth ions, and specifically Erbium ions, in the depletion layer of said P/N junction.
    The junction may be for instance the base-collector region of a bipolar transistor and is reverse biased.

    Abstract translation: 本发明涉及一种用于电光应用的半导体器件，其包括至少掺杂在半导体衬底上的稀土离子掺杂的P / N结。 该装置可以用于在硅中获得激光作用，并且包括在所述P / N结的耗尽层中获得的掺杂有稀土离子，特别是铒离子的空腔或波导和相干光源。 结可以是例如双极晶体管的基极 - 集电极区域并且被反向偏置。

    Semiconductor power device with multiple drain structure and corresponding manufacturing process
    2.
    发明公开
    Semiconductor power device with multiple drain structure and corresponding manufacturing process 审中-公开
    半导体功率器件具有多个漏极结构和相应的制造工艺

    公开(公告)号：EP2299481A2

    公开(公告)日：2011-03-23

    申请号：EP10015719.7

    申请日：2006-07-07

    Applicant: STMicroelectronics S.r.l.

    Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio ,  Rascuna, Simone

    IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

    CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

    Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps:
    - forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity of a first value of resistivity (ρ 1 ) forming the drain epitaxial layer (20) on the semiconductor substrate (100),
    - forming in the first semiconductor layer (21) first sub-regions (51) of a second type of conductivity by means of a first selective implant step with a first implant dose (Φ 1P ),
    - forming in the first semiconductor layer (21) second sub-regions (D1, D1a) of the first type of conductivity by means of a second implant step with a second implant dose (Φ 1N ),
    - forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51),
    - carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).

    Abstract translation: 用于制造集成在其上形成漏极半导体层（20）的第一导电类型的半导体衬底（100）上的多漏功率电子器件（30）的工艺，其特征在于其包括以下步骤： - 在 在所述半导体衬底（100）上形成漏极外延层（20）的第一电阻率值（ρ1）的第一导电类型的第一半导体外延层（21）， - 在所述第一半导体层（21） 借助于具有第一注入剂量（Φ1P）的第一选择性注入步骤的第二导电类型的第一子区域（51）;在第一半导体层（21）中形成第二导电类型的第二子区域（D1，D1a） 借助于具有第二注入剂量（Φ1N）的第二注入步骤的第一导电类型， - 形成表面半导体层（23），其中形成第二导电类型的本体区域（40）与第一子区域 - 区域（51）， - carryin 形成热扩散工艺，使得第一子区域（51）形成与主体区域（40）对准并电接触的单个电连续柱状区域（50）。

    MOS technology power device
    8.
    发明公开
    MOS technology power device 审中-公开
    MOS-TECHNOLOGIE-Leistungsanordnung

    公开(公告)号：EP1160873A1

    公开(公告)日：2001-12-05

    申请号：EP00830360.4

    申请日：2000-05-19

    Applicant: STMicroelectronics S.r.l.

    Inventor： Saggio, Mario ,  Frisina, Ferruccio ,  Magri', Angelo

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/36

    CPC classification number: H01L29/7802 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634

    Abstract: A MOS technology power device is described which comprises a plurality of elementary active units and apart (1) of said power device which is placed between zones where the elementary active units are formed. The part (1) of the power device comprises at least two heavily doped body regions (4) of a first conductivity type which are formed in a semiconductor layer (3) of a second conductivity type, a first lightly doped semiconductor region (5) of the first conductivity type which is placed laterally between the two body regions (4). The first semiconductor region (5) is placed under a succession of a thick silicon oxide layer (9), a polysilicon layer (10) and a metal layer (13). A plurality of second lightly doped semiconductor regions (6) of the first conductivity type are placed under said at least two heavily doped body regions (4) and under said first lightly doped semiconductor region (5) of the first conductivity type, each region (6) of said plurality of second lightly doped semiconductor regions (6) of the first conductivity type being separated from the other by portions of said semiconductor layer (3) of the second conductivity type.

    Abstract translation: 描述了一种MOS技术功率器件，其包括多个基本有源单元，并且分离（1）所述功率器件，放置在形成基本有源单元的区域之间。 功率器件的部分（1）包括形成在第二导电类型的半导体层（3）中的至少两个第一导电类型的重掺杂体区域（4），第一轻掺杂半导体区域（5） 的横向放置在两个主体区域（4）之间的第一导电类型。 第一半导体区域（5）被放置在厚氧化硅层（9），多晶硅层（10）和金属层（13）的一连串之下。 第一导电类型的多个第二轻掺杂半导体区域（6）放置在所述至少两个重掺杂体区域（4）的下方，并且位于第一导电类型的所述第一轻掺杂半导体区域（5）的下方，每个区域 所述第一导电类型的所述多个第二轻掺杂半导体区域（6）的所述第二导电类型的所述半导体层（3）的一部分与所述第二导电类型的所述多个第二轻掺杂半导体区域（6）分离。

Patent Agency Ranking