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    METHOD OF INCREASING MEMS ENCLOSURE PRESSURE USING OUTGASSING MATERIAL
    4.
    发明申请
    METHOD OF INCREASING MEMS ENCLOSURE PRESSURE USING OUTGASSING MATERIAL 有权
    使用外加材料增加MEMS外壳压力的方法

    公开(公告)号：US20170001861A1

    公开(公告)日：2017-01-05

    申请号：US15265668

    申请日：2016-09-14

    Applicant: InvenSense, Inc.

    Inventor： Cerina ZHANG ,  Martin LIM ,  Jongwoo SHIN ,  Joseph SEEGER

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/0023 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00269 ,  B81C2201/0104 ,  B81C2201/0132 ,  B81C2203/0145 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0792

    Abstract: Semiconductor manufacturing processes include providing a first substrate having a first passivation layer disposed above a patterned top-level metal layer, and further having a second passivation layer disposed over the first passivation layer; the second passivation layer has a top surface. The processes further include forming an opening in a first portion of the second passivation layer, and the opening exposes a portion of a surface of the first passivation layer. The processes further include patterning the second and first passivation layers to expose portions of the patterned top-level metal layer and bonding a second substrate and the first substrate to each other. The bonding occurs within a temperature range in which at least the exposed portion of the first passivation layer undergoes outgassing.

    Abstract translation: 半导体制造工艺包括提供第一衬底，其具有设置在图案化顶层金属层上方的第一钝化层，并且还具有设置在第一钝化层上的第二钝化层; 第二钝化层具有顶表面。 所述方法还包括在第二钝化层的第一部分中形成开口，并且开口暴露第一钝化层的表面的一部分。 所述方法还包括图案化第二钝化层和第一钝化层以暴露图案化顶层金属层的部分并将第二基板和第一基板彼此接合。 接合发生在至少第一钝化层的暴露部分经历脱气的温度范围内。

    ULTRASONIC TRANSDUCER, METHOD OF PRODUCING SAME, AND ULTRASONIC PROBE USING SAME
    6.
    发明申请
    ULTRASONIC TRANSDUCER, METHOD OF PRODUCING SAME, AND ULTRASONIC PROBE USING SAME 有权
    超声波传感器，其制造方法和使用其的超声波探头

    公开(公告)号：US20160008849A1

    公开(公告)日：2016-01-14

    申请号：US14799632

    申请日：2015-07-15

    Applicant: Hitachi Medical Corporation

    Inventor： Shuntaro MACHIDA ,  Takashi KOBAYASHI

    IPC: B06B1/02

    CPC classification number: B06B1/0292 ,  B81C1/00158 ,  B81C1/00182 ,  B81C1/00214 ,  B81C1/00476 ,  B81C1/00531 ,  B81C1/00611 ,  B81C2201/0104 ,  B81C2201/0107 ,  B81C2201/0109 ,  C09K13/00 ,  C23F4/00 ,  H01L21/30604 ,  H01L29/84 ,  Y10T29/49156

    Abstract: Disclosed is an ultrasonic transducer that is provided with: a bottom electrode; an electric connection part which is connected to the bottom electrode from the bottom of the bottom electrode; a first insulating film which is formed so as to cover the bottom electrode; a cavity which is formed on the first insulating film so as to overlap the bottom electrode when seen from above; a second insulating film which is formed so as to cover the cavity; and a top electrode which is formed on the second insulating film so as to overlap the cavity when seen from above. The electric connection part to the bottom electrode is positioned so as to not overlap the cavity when seen from above.

    Abstract translation: 公开了一种超声波换能器，其具备：底部电极; 电连接部，其从所述底部电极的底部连接到所述底部电极; 形成为覆盖底部电极的第一绝缘膜; 形成在第一绝缘膜上以便从上方观察时与底部电极重叠的空腔; 形成为覆盖空腔的第二绝缘膜; 以及形成在第二绝缘膜上以从上方观察时与空腔重叠的顶部电极。 位于底部电极的电连接部分被定位为当从上方观察时不与腔体重叠。

    METHOD OF INCREASING MEMS ENCLOSURE PRESSURE USING OUTGASSING MATERIAL
    7.
    发明申请
    METHOD OF INCREASING MEMS ENCLOSURE PRESSURE USING OUTGASSING MATERIAL 有权
    使用外加材料增加MEMS外壳压力的方法

    公开(公告)号：US20150360939A1

    公开(公告)日：2015-12-17

    申请号：US14832786

    申请日：2015-08-21

    Applicant: InvenSense, Inc.

    Inventor： Cerina Zhang ,  Martin Lim ,  Jongwoo Shin ,  Joseph Seeger

    IPC: B81C1/00

    CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/0023 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00269 ,  B81C2201/0104 ,  B81C2201/0132 ,  B81C2203/0145 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0792

    Abstract: Semiconductor manufacturing processes include providing a first substrate having a first passivation layer disposed above a patterned top-level metal layer, and further having a second passivation layer disposed over the first passivation layer; the second passivation layer has a top surface. The processes further include forming an opening in a first portion of the second passivation layer, and the opening exposes a portion of a surface of the first passivation layer. The processes further include patterning the second and first passivation layers to expose portions of the patterned top-level metal layer and bonding a second substrate and the first substrate to each other. The bonding occurs within a temperature range in which at least the exposed portion of the first passivation layer undergoes outgassing.

    Abstract translation: 半导体制造工艺包括提供第一衬底，其具有设置在图案化顶层金属层上方的第一钝化层，并且还具有设置在第一钝化层上的第二钝化层; 第二钝化层具有顶表面。 所述方法还包括在第二钝化层的第一部分中形成开口，并且开口暴露第一钝化层的表面的一部分。 所述方法还包括图案化第二钝化层和第一钝化层以暴露图案化顶层金属层的部分并将第二基板和第一基板彼此接合。 接合发生在至少第一钝化层的暴露部分经历脱气的温度范围内。

    Method and apparatus for maintaining parallelism of layers and/or achieving desired thicknesses of layers during the electrochemical fabrication of structures
    8.
    发明授权
    Method and apparatus for maintaining parallelism of layers and/or achieving desired thicknesses of layers during the electrochemical fabrication of structures 有权
    在结构的电化学制造期间保持层的平行度和/或实现所需厚度的层的方法和装置

    公开(公告)号：US08702956B2

    公开(公告)日：2014-04-22

    申请号：US13356398

    申请日：2012-01-23

    Applicant: Uri Frodis ,  Adam L. Cohen ,  Michael S. Lockard

    Inventor： Uri Frodis ,  Adam L. Cohen ,  Michael S. Lockard

    IPC: C25D5/52 ,  C25D5/10 ,  C25D5/02

    CPC classification number: C25D5/48 ,  B33Y10/00 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885 ,  Y10T156/1052

    Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.

    Abstract translation: 本发明的一些实施例提供了用于电化学制造多层结构（例如中尺度或微结构）的方法和装置，其具有改进的端点检测和用于在电化学制造过程中被平坦化的材料（例如层）的并行维护。 一些方法涉及在平坦化期间使用夹具，其确保材料的平面化平面平行于给定公差内的其它沉积平面。 一些方法涉及使用端点检测夹具，其相对于第一沉积层或相对于在制造过程期间形成的一些其它层，相对于衬底的初始表面确保沉积材料的精确高度。 在一些实施例中，平面化可以通过研磨发生，而其他实施例可以使用金刚石切片机。

    METHOD OF FORMING NON-PLANAR MEMBRANES USING CMP
    9.
    发明申请
    METHOD OF FORMING NON-PLANAR MEMBRANES USING CMP 有权
    使用CMP形成非平面膜的方法

    公开(公告)号：US20120264301A1

    公开(公告)日：2012-10-18

    申请号：US13232012

    申请日：2011-09-14

    Applicant: Andrew B. Graham ,  Gary Yama ,  Gary O'Brien

    Inventor： Andrew B. Graham ,  Gary Yama ,  Gary O'Brien

    IPC: H01L21/306

    CPC classification number: B81C1/00103 ,  B81B2203/0376 ,  B81C2201/0104

    Abstract: A method of shaping a substrate in one embodiment includes providing a first support layer, providing a first shaping pattern on the first support layer, providing a substrate on the first shaping pattern, performing a first chemical mechanical polishing (CMP) process on the substrate positioned on the first shaping pattern, and removing the once polished substrate from the first shaping pattern.

    Abstract translation: 在一个实施例中，成形衬底的方法包括提供第一支撑层，在第一支撑层上提供第一成形图案，在第一成形图案上提供衬底，在定位的衬底上执行第一化学机械抛光（CMP）工艺 在第一成形图案上，并且从第一成形图案去除一次抛光的基板。

    Method and apparatus for maintaining parallelism of layers and/or achieving desired thicknesses of layers during the electrochemical fabrication of structures
    10.
    发明授权
    Method and apparatus for maintaining parallelism of layers and/or achieving desired thicknesses of layers during the electrochemical fabrication of structures 有权
    在结构的电化学制造期间保持层的平行度和/或实现所需厚度的层的方法和装置

    公开(公告)号：US07588674B2

    公开(公告)日：2009-09-15

    申请号：US11028944

    申请日：2005-01-03

    Applicant: Uri Frodis ,  Adam L. Cohen ,  Michael S. Lockard

    Inventor： Uri Frodis ,  Adam L. Cohen ,  Michael S. Lockard

    IPC: C25D5/52

    CPC classification number: C25D5/48 ,  B33Y10/00 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885 ,  Y10T156/1052

    Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.

    Abstract translation: 本发明的一些实施例提供了用于电化学制造多层结构（例如中尺度或微结构）的方法和装置，其具有改进的端点检测和用于在电化学制造过程中被平坦化的材料（例如层）的并行维护。 一些方法涉及在平坦化期间使用夹具，其确保材料的平面化平面平行于给定公差内的其它沉积平面。 一些方法涉及使用端点检测夹具，其相对于第一沉积层或相对于在制造过程期间形成的一些其它层，相对于衬底的初始表面确保沉积材料的精确高度。 在一些实施例中，平面化可以通过研磨发生，而其他实施例可以使用金刚石切片机。

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