公开(公告)号：US08064224B2

公开(公告)日：2011-11-22

申请号：US12059133

申请日：2008-03-31

Applicant: Ravi Mahajan ,  Sandeep Sane

Inventor： Ravi Mahajan ,  Sandeep Sane

IPC: H05K7/02 ,  H01L21/78 ,  H01L21/50

CPC classification number: H05K1/142 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15192 ,  H05K1/141 ,  H05K1/181 ,  H05K1/183 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05647

Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

Abstract translation: 微电子封装包括衬底（110），嵌入衬底中的硅贴片（120），在硅贴片的第一位置处的第一互连结构（131）和在第二位置处的第二互连结构（132） 硅贴片以及将第一互连结构和第二互连结构彼此连接的硅贴片中的导电线（150）。

公开(公告)号：US20110252640A1

公开(公告)日：2011-10-20

申请号：US13166861

申请日：2011-06-23

Applicant: Michimasa Takahashi ,  Masakazu Aoyama

Inventor： Michimasa Takahashi ,  Masakazu Aoyama

IPC: H01K3/10

CPC classification number: H05K3/4691 ,  H05K1/0373 ,  H05K3/0032 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09536 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A method of manufacturing a wiring board including forming a base substrate, forming a first insulation layer on a first surface of the base substrate and a second insulating layer on a second surface of the substrate opposing the first surface, forming an IVH (Interstitial Via Hole) that penetrates the base substrate, and cutting the first insulating layer in a first area and cutting the second insulating layer in a second area offset from said first area to form a first substrate laminated to a second substrate with the base layer interposed therebetween, the second substrate having a smaller mounting area than that of the first substrate such that the first substrate extends beyond an edge of the second substrate.

Abstract translation: 一种制造布线板的方法，包括形成基底基板，在基底基板的第一表面上形成第一绝缘层，在与第一表面相对的第二表面上形成第二绝缘层，形成IVH（间隙通孔 ），其在第一区域中切割第一绝缘层，并且在与所述第一区域偏移的第二区域中切割第二绝缘层，以形成层压到第二基板上的第一基板，其中介于基板之间。 第二基板具有比第一基板的安装面积小的安装面积，使得第一基板延伸超过第二基板的边缘。

公开(公告)号：US08035979B2

公开(公告)日：2011-10-11

申请号：US12966251

申请日：2010-12-13

Applicant: Yutaka Yoshino ,  Takahiro Shirai ,  Shinji Kadono ,  Mineo Kawamoto ,  Minoru Enomoto ,  Masakatsu Goto ,  Makoto Araki ,  Naoki Toda

Inventor： Yutaka Yoshino ,  Takahiro Shirai ,  Shinji Kadono ,  Mineo Kawamoto ,  Minoru Enomoto ,  Masakatsu Goto ,  Makoto Araki ,  Naoki Toda

IPC: H05K1/18

CPC classification number: H01L23/5389 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/82039 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/023 ,  H05K1/186 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/10674 ,  Y10T29/49146 ,  H01L2924/00014

Abstract: A printed wiring board includes a built-in semiconductor element. A protective film is formed on a semiconductor element-mounted surface of a base substrate to which the built-in semiconductor element is connected to protect the semiconductor element-mounted surface excepting a mounting pad. Upper and side surfaces of the built-in semiconductor element are covered with a first insulating film formed by filling a sealing material. The first insulating film is covered with a second insulating film formed of an insulating resin melted from an insulating layer that is provided in side and upper portions of the built-in semiconductor element.

Abstract translation: 印刷电路板包括内置的半导体元件。 在与内置半导体元件连接的基底基板的半导体元件安装面上形成保护膜，以保护除了安装焊盘之外的半导体元件安装表面。 通过填充密封材料形成的第一绝缘膜覆盖内置半导体元件的上表面和侧表面。 第一绝缘膜被由设置在内置半导体元件的侧部和上部的绝缘层熔化的绝缘树脂形成的第二绝缘膜覆盖。

公开(公告)号：US08035951B2

公开(公告)日：2011-10-11

申请号：US12805886

申请日：2010-08-23

Applicant: Shih-Hsien Wu ,  Shinn-Juh Lai ,  Min-Lin Lee ,  Shur-Fen Liu

Inventor： Shih-Hsien Wu ,  Shinn-Juh Lai ,  Min-Lin Lee ,  Shur-Fen Liu

IPC: H01G4/06

CPC classification number: H01G4/06 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/14 ,  H01G4/20 ,  H01G4/206 ,  H05K1/162 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09672 ,  H05K2201/2036 ,  Y10T29/417

Abstract: A capacitor device with a capacitance is introduced. The capacitor device includes at least one capacitive element. The at least capacitive element comprises a pair of first conductive layers being opposed to each other, at least one first dielectric layer formed on a surface of at least one of the first conductive layers, and a second dielectric layer being sandwiched between the first conductive layers. The first dielectric layer has a first dielectric constant and the second dielectric layer has a second dielectric constant. The capacitance of the capacitor device depends on dielectric parameters of the first dielectric layer and the second dielectric layer. The dielectric parameters comprise the first dielectric constant and thickness of the at least one first dielectric layer and the second dielectric constant and thickness of the second dielectric layer.

Abstract translation: 引入具有电容的电容器件。 电容器装置包括至少一个电容元件。 所述至少电容元件包括彼此相对的一对第一导电层，至少一个形成在所述第一导电层中的至少一个的表面上的第一电介质层，以及夹在所述第一导电层 。 第一介电层具有第一介电常数，第二介电层具有第二介电常数。 电容器器件的电容取决于第一介电层和第二介电层的介电参数。 介电参数包括第一介电常数和至少一个第一介电层的厚度和第二介电常数和第二介电层的厚度。

公开(公告)号：US07982139B2

公开(公告)日：2011-07-19

申请号：US11356350

申请日：2006-02-17

Applicant: Takashi Kariya ,  Akira Mochida

Inventor： Takashi Kariya ,  Akira Mochida

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A multilayer printed wiring board 10 includes: a mounting portion 60 on the top surface of which is mounted a semiconductor element that is electrically connected to a wiring pattern 32, etc.; and a capacitor portion 40 having a high dielectric constant layer 43, formed of ceramic and first and second layer electrodes 41 and 42 that sandwich the high dielectric constant layer 43. One of either of the first and second layer electrodes 41 and 42 is connected to a power supply line of the semiconductor element and the other of either of the first and second layer electrodes 41 and 42 is connected to a ground line. In this multilayer printed wiring board 10, high dielectric constant layer 43 included in the layered capacitor portion 40, which is connected between the power supply line and the ground line, is formed of ceramic. With this structure, the static capacitance of the layered capacitor portion 40 can be high, and an adequate decoupling effect is exhibited even under circumstances in which instantaneous potential drops occur readily.

Abstract translation: 多层印刷电路板10包括：安装部分60，其顶表面上安装有电连接到布线图案32的半导体元件; 以及具有由陶瓷形成的高介电常数层43的电容器部分40和夹在高介电常数层43上的第一和第二层电极41和42。第一和第二层电极41和42中的一个连接到 半导体元件的电源线和第一和第二层电极41和42中的另一个连接到接地线。 在这种多层印刷电路板10中，连接在电源线和接地线之间的层状电容器部分40中包括的高介电常数层43由陶瓷形成。 利用这种结构，层状电容器部分40的静态电容可以很高，并且即使在容易发生瞬时电位下降的情况下也可以发挥足够的去耦效应。

公开(公告)号：US07982135B2

公开(公告)日：2011-07-19

申请号：US11927144

申请日：2007-10-29

Applicant: Michimasa Takahashi ,  Masakazu Aoyama

Inventor： Michimasa Takahashi ,  Masakazu Aoyama

IPC: H05K1/00

CPC classification number: H05K3/4691 ,  H05K1/0218 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4664 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/096 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A flex-rigid wiring board includes a flexible board including a flexible substrate and a conductor pattern formed over the flexible substrate, a non-flexible substrate disposed adjacent to the flexible board, an insulating layer including an inorganic material and covering the flexible board and the non-flexible substrate, the insulating layer exposing at least one portion of the flexible board, a conductor pattern formed on the insulating layer, and a plating layer connecting the conductor pattern of the flexible board and the conductor pattern on the insulating layer.

Abstract translation: 弹性刚性布线板包括柔性基板，该柔性基板包括柔性基板和形成在柔性基板上的导体图案，邻近柔性基板设置的非柔性基板，包括无机材料并覆盖柔性基板的绝缘层和 非柔性基板，绝缘层暴露柔性板的至少一部分，形成在绝缘层上的导体图案，以及将柔性基板的导体图案与导体图案连接在绝缘层上的镀层。

公开(公告)号：US20110100680A1

公开(公告)日：2011-05-05

申请号：US12793720

申请日：2010-06-04

Applicant: Nobuyuki NAGANUMA

Inventor： Nobuyuki NAGANUMA

IPC: H05K1/00 ,  H05K3/36

CPC classification number: H05K1/142 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4694 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/2036 ,  H05K2203/173

Abstract: A wiring board has a first rigid wiring board having a first wiring layer on a first main surface, a second rigid wiring board having a second wiring layer on a second main surface, a first connection portion connecting the first wiring layer and the second wiring layer, and a first interlayer insulation layer formed on the first wiring layer, the second wiring layer and the first connection portion. In such a wiring board, the first rigid wiring board and the second rigid wiring board are positioned in such a way that the first main surface and the second main surface are set at substantially the same level, and the first wiring layer and the second wiring layer are electrically connected by the first connection portion.

Abstract translation: 布线基板具有：第一刚性布线基板，在第一主面上具有第一布线层，第二刚性布线板，在第二主面上具有第二布线层;第一连接部，其将第一布线层和第二布线层 以及形成在第一布线层，第二布线层和第一连接部上的第一层间绝缘层。 在这种布线板中，第一刚性布线板和第二刚性布线板以第一主表面和第二主表面设置在大致相同的水平的方式定位，并且第一布线层和第二布线 层通过第一连接部电连接。

公开(公告)号：US07915538B2

公开(公告)日：2011-03-29

申请号：US12021548

申请日：2008-01-29

Applicant: Masamitsu Ikumo ,  Tadahiro Okamoto ,  Eiji Watanabe

Inventor： Masamitsu Ikumo ,  Tadahiro Okamoto ,  Eiji Watanabe

IPC: H05K1/03

CPC classification number: H01L23/5385 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/13 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/20 ,  H05K3/28 ,  H05K3/4682 ,  H05K2201/0187 ,  H05K2201/09036 ,  H05K2201/09518 ,  H05K2203/016 ,  Y10T29/49126 ,  Y10T428/24802 ,  Y10T428/24917 ,  H01L2224/0401

Abstract: A multilayer wiring board having a plurality of wiring boards in which wiring layers and resin layers in each wiring board are alternately arranged in a laminated formation. In the multilayer wiring board, all the resin layers and the wiring layers, except a resin layer in the plurality of wiring boards, are separated in a same position between the plurality of wiring boards and the resin layer is continuous in the same position.

Abstract translation: 具有多个配线基板的多层布线基板，其中布线层和每个布线板中的树脂层交替地布置在层叠结构中。 在多层布线基板中，除了多个布线基板中的树脂层以外的所有树脂层和布线层在多个布线基板之间的相同位置分离，并且树脂层在相同位置连续。

公开(公告)号：US20110067917A1

公开(公告)日：2011-03-24

申请号：US12654526

申请日：2009-12-22

Applicant: Dae-Hyun Park ,  Han Kim ,  Kang-Wook Bong

Inventor： Dae-Hyun Park ,  Han Kim ,  Kang-Wook Bong

IPC: H05K9/00

CPC classification number: H05K1/0236 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K1/0231 ,  H05K1/024 ,  H05K2201/0187 ,  H05K2201/09627 ,  H05K2201/09881 ,  H01L2924/00014

Abstract: Disclosed is a printed circuit board including an electromagnetic bandgap structure. The electromagnetic bandgap structure, which includes a first dielectric material for interlayer insulation and is for blocking a noise, is inserted into the printed circuit board. The electromagnetic bandgap structure can include a first conductive plate, a second conductive plate arranged on a planar surface that is different from that of the first conductive plate, a third conductive plate arranged on a same planar surface as the first conductive plate, and a stitching via unit configured to connect the first conductive plate and the third conductive plate through the planar surface on which the second conductive plate is arranged. A second dielectric material having a permittivity that is different from that of the first dielectric material is interposed between any two of the first conductive plate, the second conductive plate, and the third conductive plate.

Abstract translation: 公开了一种包括电磁带隙结构的印刷电路板。 包括用于层间绝缘并用于阻挡噪声的第一介电材料的电磁带隙结构被插入到印刷电路板中。 电磁带隙结构可以包括第一导电板，布置在与第一导电板不同的平面上的第二导电板，布置在与第一导电板相同的平坦表面上的第三导电板，以及缝合 通孔单元被配置为通过其上布置有第二导电板的平面连接第一导电板和第三导电板。 具有不同于第一介电材料的介电常数的第二介电材料插入在第一导电板，第二导电板和第三导电板中的任何两个之间。

公开(公告)号：US20110061922A1

公开(公告)日：2011-03-17

申请号：US12610166

申请日：2009-10-30

Applicant: Jae Joon LEE ,  Jin Yong Ahn ,  Jin Ho Kim ,  Dong Ju Jeon

Inventor： Jae Joon LEE ,  Jin Yong Ahn ,  Jin Ho Kim ,  Dong Ju Jeon

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K1/0271 ,  H01L23/13 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/20 ,  H05K3/4682 ,  H05K2201/0187 ,  H05K2201/068 ,  H05K2201/09136 ,  H05K2201/2018 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Disclosed is a package substrate, which includes an insulating layer including a circuit layer having a via for connecting layers and an insulating member formed in the insulating layer so as to separate the insulating layer, thus preventing the package substrate from warping and reducing land co-planarity of the substrate. A method of fabricating the package substrate is also provided, including (a) forming a first circuit layer on a carrier, (b) forming an insulating layer on the carrier having the first circuit layer, (c) forming an insulating member in the insulating layer so as to separate the insulating layer, (d) forming a second circuit layer including a via on the insulating layer and the insulating member, and (e) removing the carrier.

Abstract translation: 公开了一种封装基板，其包括绝缘层，该绝缘层包括具有用于连接层的通孔的电路层和形成在绝缘层中的绝缘构件，以分离绝缘层，从而防止封装基板翘曲并减少焊盘共面， 基底的平面度。 还提供了一种制造封装衬底的方法，包括：（a）在载体上形成第一电路层，（b）在具有第一电路层的载体上形成绝缘层，（c）在绝缘层中形成绝缘构件 层，以分离绝缘层，（d）在绝缘层和绝缘构件上形成包括通孔的第二电路层，以及（e）去除载体。