公开(公告)号：US20040262742A1

公开(公告)日：2004-12-30

申请号：US10876897

申请日：2004-06-25

Applicant: Tessera, Inc.

Inventor： Thomas H. DiStefano ,  John W. Smith ,  Tony Faraci

IPC: H01L023/10 ,  H01L023/34 ,  H01L023/02 ,  H01L023/04

CPC classification number: H01L21/4839 ,  H01L23/22 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/642 ,  H01L24/72 ,  H01L2224/16225 ,  H01L2224/45124 ,  H01L2224/73253 ,  H01L2224/81904 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/118 ,  H05K3/361 ,  H05K3/4084 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2203/063 ,  H01L2924/00 ,  H01L2224/48

Abstract: A packaged semiconductor chip including the chip, and a package element such as a heat sink is made by connecting flexible leads between contacts on the chip and terminals on a dielectric element such as a sheet or plate and moving the sheet or plate away from the chip, and injecting a liquid material to form a compliant layer filling the space between the package element and the dielectric element, and surrounding the leads. The dielectric element and package element extend outwardly beyond the edges of the chip, and physically protect the chip. The assembly may be handled and mounted by conventional surface mounting techniques. The assembly may include additional circuit elements such as capacitors used in conjunction with the chip.

Abstract translation: 包括芯片的封装半导体芯片和诸如散热器的封装元件通过将芯片上的触点之间的柔性引线和诸如片材或板之类的电介质元件上的端子连接并将片或板远离芯片 并且注入液体材料以形成填充封装元件和电介质元件之间的空间并且围绕引线的柔性层。 介质元件和封装元件向外延伸超过芯片的边缘，并物理保护芯片。 组件可以通过常规的表面安装技术来处理和安装。 组件可以包括附加电路元件，例如与芯片结合使用的电容器。

公开(公告)号：US20040201390A1

公开(公告)日：2004-10-14

申请号：US10832483

申请日：2004-04-26

Inventor： Warren M. Farnworth ,  Salman Akram

IPC: G01R031/02

CPC classification number: H05K3/326 ,  G01R1/0466 ,  G01R31/2853 ,  H05K1/118 ,  H05K3/4092 ,  H05K2201/0373 ,  H05K2201/0397 ,  H05K2201/09036 ,  H05K2201/09081 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/4914 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a pattern of leads cantilevered over the recess configured to electrically engage a bumped contact. The leads are adapted to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the leads can include projections for penetrating the bumped contacts, a non-bonding outer layer for preventing bonding to the bumped contacts, and a curved shape which matches a topography of the bumped contacts. The leads can be formed by forming a patterned metal layer on the substrate, by attaching a polymer substrate with the leads thereon to the substrate, or be etching the substrate to form conductive beams.

Abstract translation: 用于测试半导体部件的互连件包括基板和基板上的触点，用于与部件上的凸起触点进行临时电连接。 每个接触件包括一个凹部和悬在该凹部上的引线图案，其构造成电接合凸起的触点。 引线适于在凹部内在z方向上移动以适应凸起接触件的高度和平面度的变化。 此外，引线可以包括用于穿透凸起的触点的突起，用于防止与凸起的触点接合的非结合外层以及与凸起的触点的形状相匹配的弯曲形状。 可以通过在基板上形成图案化的金属层，通过将聚合物基板与其上的引线附接到基板上，或者蚀刻基板以形成导电梁来形成引线。

公开(公告)号：US20040161626A1

公开(公告)日：2004-08-19

申请号：US10724219

申请日：2003-12-01

Inventor： Soon Bog Kwon ,  Sang Hun Lee ,  Yang Sik Moon ,  Ki Pyo Hong ,  Yoon Kuen Cho

IPC: B21F001/00

CPC classification number: H05K3/244 ,  H01L23/49572 ,  H01L23/49582 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K3/28 ,  H05K2201/0397 ,  H05K2203/1105 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T29/4916 ,  Y10T428/24917 ,  Y10T428/325 ,  H01L2924/00

Abstract: A tape substrate including an insulating film, a copper foil pattern formed on the insulating film at one side of the insulating film, and provided with a connecting area where an electronic element is to be mounted, a barrier layer plated on the copper foil pattern at the connecting area, and formed with a plurality of pores, and a tin layer plated on the barrier layer, and alloyed with a portion of the copper foil pattern corresponding to the connecting area, through the pores. A method for fabricating the tape substrate is also disclosed. In accordance with the invention, it is possible to reduce the time taken for the copper foil pattern to come into contact with the electroless tin plating solution used in the tin plating process, thereby preventing the copper component of the copper foil pattern from being eluted. Accordingly, there is no open-circuit fault caused by formation of pores. The barrier layer makes it possible to obtain an improved plating efficiency and to reduce the thickness of the alloy layer. In addition, the barrier layer serves to reduce internal stress generated at the interface between the tin layer and the copper foil pattern, thereby suppressing formation of voids. Accordingly, there is an effect of preventing a short circuit caused by the growth of whiskers.

Abstract translation: 一种带状基板，包括绝缘膜，在绝缘膜的一侧上的绝缘膜上形成的铜箔图案，并且设置有要安装电子元件的连接区域，镀在铜箔图案上的阻挡层 连接区域，并且形成有多个孔，以及镀在阻挡层上的锡层，并且与对应于连接区域的铜箔图案的一部分合金化。 还公开了一种用于制造带基材的方法。 根据本发明，可以减少铜箔图案与镀锡工艺中使用的化学镀锡溶液接触所花费的时间，从而防止铜箔图案的铜成分被洗脱。 因此，没有由孔形成引起的开路故障。 阻挡层可以获得提高的电镀效率并减小合金层的厚度。 此外，阻挡层用于减少在锡层和铜箔图案之间的界面处产生的内应力，从而抑制空隙的形成。 因此，存在防止晶须生长引起的短路的效果。

公开(公告)号：US06765288B2

公开(公告)日：2004-07-20

申请号：US10236442

申请日：2002-09-06

Applicant: Philip Damberg

Inventor： Philip Damberg

IPC: H01L2304

CPC classification number: H05K3/363 ,  H01L23/5385 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06579 ,  H01L2924/00014 ,  H05K1/141 ,  H05K1/189 ,  H05K3/326 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/049 ,  H01L2224/05599

Abstract: A first microelectronic element such as a semiconductor chip is mounted to a circuit board using an adaptor which has a region extending beneath the first microelectronic element and an additional region which may be folded over the first microelectronic element or which may project laterally from the first microelectronic element. The adaptor includes a functional element in the additional region, such as a further microelectronic element or an array of terminals for mounting another element. The assembly provides the benefits of a stacked chip assembly or other mustachio module, but can be made without the need for a special prepackaged stacked chip assembly. The adaptor can be configured so that it does not materially increase the height of the first microelectronic element above the circuit board.

公开(公告)号：US06751860B2

公开(公告)日：2004-06-22

申请号：US10229288

申请日：2002-08-28

Applicant: Yuichi Watanabe ,  Hisashi Ohtsuki

Inventor： Yuichi Watanabe ,  Hisashi Ohtsuki

IPC: H05K300

CPC classification number: H05K3/041 ,  H05K3/202 ,  H05K3/3447 ,  H05K3/4092 ,  H05K2201/0382 ,  H05K2201/0397 ,  H05K2201/09118 ,  Y10T29/49147 ,  Y10T29/49151 ,  Y10T29/49153

Abstract: The present invention provides a method of making an electronic parts mounting board, comprising the steps of: punching a conductive sheet to form a circuit pattern portion and through-holes in which electronic parts are to be mounted by use of a progressive die device while at the same time partially folding said circuit pattern portion to form connection terminal portions by use of said same progressive die device; and molding an insulative resin over the whole opposite sides of said circuit pattern portion and the base ends of the terminal portions including the folded parts thereof to form an integral covering portion having openings for electrically connecting said circuit pattern portion to electronic parts to be mounted thereon.

Abstract translation: 本发明提供一种制造电子部件安装板的方法，包括以下步骤：在导电片上冲压导电片以形成电路图案部分和通过使用渐进式模具装置安装电子部件的通孔，同时在 同时部分地折叠所述电路图形部分以通过使用所述相同的渐进式模具装置形成连接端子部分; 以及在所述电路图形部分的整个相对侧和包括其折叠部分的端子部分的基端部上模制绝缘树脂以形成具有用于将所述电路图案部分电连接到要安装在其上的电子部件的开口的整体覆盖部分。

公开(公告)号：US20040058470A1

公开(公告)日：2004-03-25

申请号：US10668925

申请日：2003-09-23

Inventor： Robert L. Canella

IPC: H01L021/44 ,  H01L021/50 ,  H01L021/48

CPC classification number: H01L24/90 ,  G01R1/0408 ,  G01R1/0466 ,  H01L21/283 ,  H01L21/2885 ,  H01L21/4846 ,  H01L21/67121 ,  H01L23/49811 ,  H01L24/72 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/326 ,  H05K3/4092 ,  H05K2201/0311 ,  H05K2201/0397 ,  H05K2201/09063 ,  H05K2201/10734 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49156 ,  Y10T29/49169 ,  Y10T29/49181 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A substrate assembly including a substrate and a plurality of spring-biased electrical contacts formed thereon for establishing electrical contact with the lead elements of an IC device. The substrate assembly also comprises a layer of resilient conductive material formed on a surface of the substrate, the spring-biased electrical contacts being formed in the resilient conductive material layer in situ on the substrate. Each spring-biased electrical contact includes a surface or surfaces configured to bias against and electrically contact an IC device lead element. The present invention also encompasses methods of fabricating substrate assemblies according to the invention, including heat treating the substrate assembly after formation to achieve desired spring characteristics.

Abstract translation: 一种衬底组件，包括衬底和形成在其上的多个弹簧偏置电触点，用于与IC器件的引线元件建立电接触。 衬底组件还包括形成在衬底的表面上的弹性导电材料层，弹簧偏压的电触点在衬底上原位形成在弹性导电材料层中。 每个弹簧偏置的电触点包括被配置为偏置IC电气元件引线元件并与其电接触的表面或表面。 本发明还包括制造根据本发明的衬底组件的方法，包括在形成之后对衬底组件进行热处理以实现期望的弹簧特性。

公开(公告)号：US20040045159A1

公开(公告)日：2004-03-11

申请号：US10658941

申请日：2003-09-10

Applicant: Tessera, Inc.

Inventor： Thomas H. DiStefano ,  Joseph Fjelstad

IPC: C09J001/00

CPC classification number: H05K3/462 ,  H01L23/49827 ,  H01L23/5385 ,  H01L2924/0002 ,  H01R12/523 ,  H01R12/714 ,  H01R13/2414 ,  H01R43/0256 ,  H05K1/0272 ,  H05K1/036 ,  H05K1/056 ,  H05K1/116 ,  H05K3/0032 ,  H05K3/326 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/0382 ,  H05K2201/0397 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2203/0554 ,  H05K2203/0582 ,  H05K2203/135 ,  H05K2203/308 ,  Y10T29/49126 ,  Y10T29/49133 ,  Y10T29/49137 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1744 ,  H01L2924/00

Abstract: An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact extends from a central conductor, and has a peripheral portion adapted to contract radially inwardly toward the central conductor response to a force applied by a contact pad defining a central hole on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts contract radially inwardly and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by friction welding, or by a conductive bonding material carried on the contacts themselves.

公开(公告)号：US06699395B1

公开(公告)日：2004-03-02

申请号：US09690560

申请日：2000-10-18

Applicant: John W. Svenkeson ,  John D. Hamre

Inventor： John W. Svenkeson ,  John D. Hamre

IPC: H05K300

CPC classification number: H05K3/0032 ,  H01R12/78 ,  H01R12/85 ,  H05K1/118 ,  H05K3/365 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2201/09063 ,  H05K2203/0554 ,  H05K2203/167 ,  Y10T29/49156

Abstract: A method of forming a conductive device includes forming a conductive layer on a substrate; etching the conductive layer to form a plurality of conductive traces; etching the conductive layer to form at least one mask feature; and removing substrate material that is not covered by the at least one mask feature so as to form at least one mechanical alignment feature.

Abstract translation: 形成导电器件的方法包括在衬底上形成导电层; 蚀刻导电层以形成多个导电迹线; 蚀刻导电层以形成至少一个掩模特征; 以及去除未被所述至少一个掩模特征覆盖的基板材料，以便形成至少一个机械对准特征。

公开(公告)号：US06518672B2

公开(公告)日：2003-02-11

申请号：US09880978

申请日：2001-06-14

Applicant: Takashi Kurihara ,  Michio Horiuchi ,  Shigeru Mizuno ,  Yuka Tamadate

Inventor： Takashi Kurihara ,  Michio Horiuchi ,  Shigeru Mizuno ,  Yuka Tamadate

IPC: H01L2348

CPC classification number: H05K3/363 ,  H01L23/49805 ,  H01L23/4985 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H05K1/144 ,  H05K2201/0397 ,  H05K2201/10681

Abstract: A multi-layer wiring substrate comprises: a plurality of wiring substrates, each of the substrates comprising a plate or sheet-like insulating layer and a wiring layer formed on only one of surfaces of the insulating layer; the plurality of wiring substrates being laminated in such a manner that the insulating layer and wiring layer are alternately arranged; at least a pair of said wiring layers arranged on respective surfaces of the insulating layer being electrically connected with each other by means of connecting portions formed so as to pass through the insulating layer; and the connecting portion comprises a part of the wiring layer which is extended into a region of an opening formed so as to pass through said insulating layer and a low-melting point metal disposed in the opening and electrically connecting the part of the wiring layer with a wiring substrate formed on an adjacent insulating layer of the laminated structure.

Abstract translation: 多层布线基板包括：多个布线基板，每个基板包括板或片状绝缘层和仅形成在绝缘层的一个表面上的布线层; 所述多个布线基板以使得所述绝缘层和布线层交替布置的方式层叠; 布置在绝缘层的各个表面上的至少一对所述布线层通过形成为穿过绝缘层的连接部彼此电连接; 并且所述连接部分包括延伸到形成为穿过所述绝缘层的开口的区域中的所述布线层的一部分和布置在所述开口中的低熔点金属，并且将所述布线层的所述部分与 形成在叠层结构的相邻绝缘层上的布线基板。

公开(公告)号：US20030027374A1

公开(公告)日：2003-02-06

申请号：US10255297

申请日：2002-09-26

Inventor： Zlata Kovac ,  Craig S. Mitchell ,  Thomas H. DiStefano ,  John W. Smith

IPC: H01L021/58

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/72 ,  H01L24/75 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75301 ,  H01L2224/81801 ,  H01L2224/83136 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/118 ,  H05K3/361 ,  H05K3/4084 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2203/063 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49174 ,  H01L2924/00014

Abstract: A method of making a microelectronic assembly including a compliant interface includes providing a first support structure, such as a flexible dielectric sheet, having a first surface and a porous resilient layer on the first surface of the first support structure, stretching the first support structure and bonding the stretched first support structure to a ring structure. The first surface of a second support structure, such as a semiconductor wafer, is then abutted against the porous layer and, desirably after the abutting step, a first curable liquid is disposed between the first and second support structures and within the porous layer. The first curable liquid may then be at least partially cured.