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    Wired circuit board
    94.
    发明申请
    Wired circuit board 失效
    有线电路板

    公开(公告)号：US20080087455A1

    公开(公告)日：2008-04-17

    申请号：US11902556

    申请日：2007-09-24

    Applicant: Szu-Han Hu ,  Voon Ho ,  Hiroshi Yamazaki ,  Martin McCaslin

    Inventor： Szu-Han Hu ,  Voon Ho ,  Hiroshi Yamazaki ,  Martin McCaslin

    IPC: H01B7/00

    CPC classification number: H05K1/0221 ,  H05K1/117 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/09481 ,  H05K2201/09809 ,  H05K2203/0733

    Abstract: A wired circuit board has a plurality of insulating layers, a conductive layer having a signal wiring extending in a longitudinal direction which is covered with the insulating layers, and a signal connecting terminal provided on a longitudinal end of the signal wiring and exposed from the insulating layers, and a ground layer having a ground wiring covered with the insulating layers and formed to surround the signal wiring in a perpendicular direction to the longitudinal direction, and a ground connecting terminal provided on a longitudinal end of the ground wiring and exposed from the insulating layers. The signal connecting terminal and the ground connecting terminal are formed on an upper surface of the same insulating layer among the plurality of the insulating layers.

    Abstract translation: 布线电路板具有多个绝缘层，导电层具有沿纵向方向延伸并被绝缘层覆盖的信号布线，以及信号连接端子，设置在信号布线的纵向端并从绝缘层 以及接地层，其具有覆盖有绝缘层的接地布线，并且形成为围绕与纵向方向垂直的方向的信号布线;以及接地端子，其设置在接地布线的纵向端部并从绝缘体 层。 信号连接端子和接地连接端子形成在多个绝缘层中的相同绝缘层的上表面上。

    Semiconductor device
    95.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：US20080079138A1

    公开(公告)日：2008-04-03

    申请号：US11898967

    申请日：2007-09-18

    Applicant: Norio Takahashi

    Inventor： Norio Takahashi

    IPC: H01L23/48

    CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K3/0044 ,  H05K3/4611 ,  H05K3/4697 ,  H05K2201/09481 ,  H05K2201/10969 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A semiconductor device that mounts a semiconductor chip in a multilayer substrate, including, inner layer conductive patterns formed in the multilayer substrate; extending conductive portions formed to extend on inner layer conductive patterns in the thickness direction, in the chip mounting area into which the semiconductor chip is mounted; and a cutout portion that is formed by cutting the multilayer substrate, and into which the semiconductor chip is contained, in the chip mounting area. And, in the cutout portion, the underside surface of the semiconductor chip and the inner layer conductive patterns are connected via the extending conductive portions at a same potential.

    Abstract translation: 一种半导体器件，其将半导体芯片安装在多层基板中，包括形成在所述多层基板中的内层导电图案; 在半导体芯片安装在芯片安装区域中，在厚度方向的内层导电图案上形成延伸的导电部分; 以及切屑部，其通过在所述芯片安装区域中切割所述多层基板而形成有所述半导体芯片。 并且，在切口部分中，半导体芯片的下表面和内层导电图案经由延伸的导电部分以相同的电位连接。

    METHOD AND APPARATUS FOR SUPPLYING POWER TO A SEMICONDUCTOR DEVICE USING A CAPACITOR DC SHUNT
    96.
    发明申请
    METHOD AND APPARATUS FOR SUPPLYING POWER TO A SEMICONDUCTOR DEVICE USING A CAPACITOR DC SHUNT 失效
    使用电容器DC SHUNT向半导体器件供电的方法和装置

    公开(公告)号：US20080079136A1

    公开(公告)日：2008-04-03

    申请号：US11943468

    申请日：2007-11-20

    Applicant: Yuan-Liang Li

    Inventor： Yuan-Liang Li

    IPC: H01L23/48 ,  H01L21/60

    CPC classification number: H05K1/0231 ,  H01L2224/16225 ,  H05K1/0206 ,  H05K1/0212 ,  H05K1/145 ,  H05K3/3494 ,  H05K2201/09481 ,  H05K2201/10325 ,  H05K2201/10515 ,  H05K2201/10734

    Abstract: A power shunt for use within a semiconductor device of a type having a motherboard and an integrated circuit package electrically coupled to the motherboard and of a type having a spaced portion located between the motherboard and the package. The power shunt comprises a capacitor within the spaced portion between the motherboard and the package of the semiconductor device. The capacitor includes a conductive layer of a first type, a conductive layer of a second type, and a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer, wherein said first type conductive layer and second type conductive layer form a conductive bridge between the motherboard and the package. The arrangement of the capacitor fulfills the dual function of providing decoupling capacitance with the capability of supplying an additional path of current between the motherboard and package to the die load 16.

    Abstract translation: 一种用于半导体器件的功率分流器，该半导体器件具有电耦合到母板的主板和集成电路封装，并且具有位于母板和封装之间的间隔部分的类型。 功率分流器包括在母板和半导体器件的封装之间的间隔部分内的电容器。 电容器包括第一类型的导电层，第二类型的导电层和将第一类型导电层与第二类型导电层电隔离的电介质层，其中所述第一导电层和第二导电层形成 主板和封装之间的导电桥。 电容器的布置实现了提供去耦电容的双重功能，其具有在母板和封装之间向芯片负载16提供额外的电流路径的能力。

    Flip chip substrate structure and the method for manufacturing the same
    97.
    发明申请
    Flip chip substrate structure and the method for manufacturing the same 审中-公开
    倒装芯片基板结构及其制造方法

    公开(公告)号：US20080060838A1

    公开(公告)日：2008-03-13

    申请号：US11519896

    申请日：2006-09-13

    Applicant: Bo-Wei Chen ,  Hsien-Shou Wang ,  Shih-Ping Hsu

    Inventor： Bo-Wei Chen ,  Hsien-Shou Wang ,  Shih-Ping Hsu

    IPC: H05K1/11 ,  H01R12/04

    CPC classification number: H05K3/4682 ,  H01L21/4857 ,  H01L21/68 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K3/205 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/099 ,  H05K2203/0384 ,  H01L2924/00

    Abstract: A flip chip substrate structure and a method to fabricate thereof are disclosed. The structure comprises a build up structure, a first solder mask and a second solder mask. Plural first and second electrical contact pads are formed on the first and second surface of the build up structure, respectively. A first solder mask having plural openings is formed on the first surface of the build up structure, and the openings expose the first electrical contact pads, wherein the aperture of the openings of the first solder mask are equal to the outer diameter of the first electrical contact pads. A second solder mask having plural openings is formed on the second surface of the build up structure, and the openings expose the second electrical contact pads, wherein the aperture of the openings of the second solder mask are smaller than the outer diameter of the second electrical contact pads.

    Abstract translation: 公开了倒装芯片基板结构及其制造方法。 该结构包括建立结构，第一焊接掩模和第二焊接掩模。 分别在堆积结构的第一和第二表面上形成多个第一和第二电接触焊盘。 具有多个开口的第一焊料掩模形成在构建结构的第一表面上，并且开口暴露第一电接触焊盘，其中第一焊接掩模的开口的孔径等于第一电接触焊盘的外径 接触垫 具有多个开口的第二焊料掩模形成在构建结构的第二表面上，并且开口暴露第二电接触焊盘，其中第二焊接掩模的开口的孔径小于第二电接触焊盘的外径 接触垫

    PACKAGE SUBSTRATE
    98.
    发明申请
    PACKAGE SUBSTRATE 有权
    包装基板

    公开(公告)号：US20080036058A1

    公开(公告)日：2008-02-14

    申请号：US11533765

    申请日：2006-09-20

    Applicant: David C. H. Cheng

    Inventor： David C. H. Cheng

    IPC: H01L23/02

    CPC classification number: H01L23/49833 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/056 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/10674 ,  H01L2224/0401

    Abstract: A package substrate including a circuit board, a reinforcing plate and at least one conductive channel is provided. A first surface of the reinforcing plate is disposed on the circuit board for resisting the warpage of the circuit board. The reinforcing plate has an opening corresponding to a first contact of the circuit board exposed thereon. In addition, one end of the conductive channel is located in the opening and electrically connected to the first contact, and the other end of the conductive channel is located on a second surface of the reinforcing plate to form a bonding pad.

    Abstract translation: 提供了包括电路板，加强板和至少一个导电通道的封装基板。 加强板的第一表面设置在电路板上以抵抗电路板的翘曲。 加强板具有对应于暴露在其上的电路板的第一接触件的开口。 此外，导电通道的一端位于开口中并电连接到第一触点，导电通道的另一端位于加强板的第二表面上以形成接合焊盘。

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