公开(公告)号：US20100155130A1

公开(公告)日：2010-06-24

申请号：US12713249

申请日：2010-02-26

Applicant: Michimasa Takahashi ,  Yukinobu Mikado ,  Takenobu Nakamura ,  Masakazu Aoyama

Inventor： Michimasa Takahashi ,  Yukinobu Mikado ,  Takenobu Nakamura ,  Masakazu Aoyama

IPC: H05K1/11

CPC classification number: H05K3/421 ,  H05K1/115 ,  H05K3/423 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09709 ,  H05K2201/09863 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/31511

Abstract: A multilayer printed wiring board comprises insulating layers and conductor layers being stacked alternately on each other. The conductor layers are electrically connected to each other through viaholes formed in the insulating layers. Each of the viaholes is formed to bulge in a direction generally orthogonal to the direction of thickness of the insulating layer. The multilayer printed wiring board is to have electronic components such as a capacitor, IC and the like mounted on the surface layer thereof.

Abstract translation: 多层印刷布线板包括彼此交替堆叠的绝缘层和导体层。 导体层通过形成在绝缘层中的通孔彼此电连接。 每个通孔形成为沿与绝缘层的厚度方向大致正交的方向凸出。 该多层印刷线路板具有安装在其表面层上的诸如电容器，IC等的电子部件。

公开(公告)号：US07552531B2

公开(公告)日：2009-06-30

申请号：US10367711

申请日：2003-02-19

Applicant: Masaru Takada ,  Kiyotaka Tsukada ,  Hiroyuki Kobayashi ,  Hisashi Minoura ,  Yoshikazu Ukai ,  Mitsuhiro Kondo

Inventor： Masaru Takada ,  Kiyotaka Tsukada ,  Hiroyuki Kobayashi ,  Hisashi Minoura ,  Yoshikazu Ukai ,  Mitsuhiro Kondo

IPC: H01K3/10

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A method of producing a printed wiring board comprising innerlayer conductor circuits among insulating layers and blind via-holes formed by irradiating laser beams from the outermost surface of the insulating layer toward the innerlayer conductor circuit. A central portion of the innerlayer conductor circuit contains a previously formed opening hole located at the bottom of the blind via-hole. Thereafter, a metal plated film is formed on surfaces of the innerlayer conductor circuits and the blind via-holes.

Abstract translation: 一种印刷电路板的制造方法，其特征在于，在由绝缘层的最表面向内层导体电路照射激光而形成绝缘层和盲孔的内层导体电路。 内层导体电路的中心部分包​​含位于盲孔通孔底部的预先形成的开孔。 此后，在内层导体电路和盲孔通孔的表面上形成金属镀膜。

公开(公告)号：US20070154741A1

公开(公告)日：2007-07-05

申请号：US11480851

申请日：2006-07-06

Applicant: Michimasa Takahashi ,  Yukinobu Mikado ,  Takenobu Nakamura ,  Masakazu Aoyama

Inventor： Michimasa Takahashi ,  Yukinobu Mikado ,  Takenobu Nakamura ,  Masakazu Aoyama

IPC: B32B27/00 ,  B32B15/08 ,  H05K1/00

CPC classification number: H05K3/421 ,  H05K1/115 ,  H05K3/423 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09709 ,  H05K2201/09863 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/31511

Abstract: A multilayer printed wiring board comprises insulating layers and conductor layers being stacked alternately on each other. The conductor layers are electrically connected to each other through viaholes formed in the insulating layers. Each of the viaholes is formed to bulge in a direction generally orthogonal to the direction of thickness of the insulating layer. The multilayer printed wiring board is to have electronic components such as a capacitor, IC and the like mounted on the surface layer thereof.

Abstract translation: 多层印刷布线板包括彼此交替堆叠的绝缘层和导体层。 导体层通过形成在绝缘层中的通孔彼此电连接。 每个通孔形成为沿与绝缘层的厚度方向大致正交的方向凸出。 该多层印刷线路板具有安装在其表面层上的诸如电容器，IC等的电子部件。

公开(公告)号：US20050155792A1

公开(公告)日：2005-07-21

申请号：US10505094

申请日：2003-02-21

Applicant: Shoji Ito ,  Osamu Nakao ,  Reiji Higuchi ,  Masahiro Okamoto

Inventor： Shoji Ito ,  Osamu Nakao ,  Reiji Higuchi ,  Masahiro Okamoto

IPC: H05K3/38 ,  H05K3/40 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K3/4617 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0394 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0191 ,  H05K2203/1453 ,  Y10T29/49165 ,  Y10T428/12181 ,  Y10T428/24917

Abstract: A multilayer wiring board assembly component comprises: an insulating substrate component (the insulating resin layer 111); a conductive layer 112 formed on one surface of said insulating substrate component 111 in the form of an electrode pattern; an adhesive layer 113 formed on the other surface of said insulating substrate component 111; and a conductive resin composition 115 with which is filled a through hole passing through said insulating substrate component 111, said adhesive layer and said conductive layer in order to make interlayer interconnection. The bore diameter of the conductive layer portion 114b of the through hole 114 is smaller than the bore diameter of the insulating resin layer portion and the adhesive layer portion 114a to establish electrical connection between the conductive resin composition 115 and the conductive layer 112 by the rare surface 112a of the conductive layer 112.

Abstract translation: 多层布线基板组件包括：绝缘基板部件（绝缘树脂层111）。 以电极图案的形式形成在所述绝缘基板部件111的一个表面上的导电层112; 形成在所述绝缘基板部件111的另一个表面上的粘合层113; 以及导电树脂组合物115，其填充有穿过所述绝缘基板部件111，所述粘合剂层和所述导电层的通孔，以形成层间互连。 通孔114的导电层部分114b的孔径小于绝缘树脂层部分和粘合剂层部分114a的孔径，以通过以下方式建立导电树脂组合物115和导电层112之间的电连接： 导电层112的稀有表面112a。

公开(公告)号：US06708873B2

公开(公告)日：2004-03-23

申请号：US10191378

申请日：2002-07-08

Applicant: Peter A. Gruber ,  Frederic Maurer ,  Lubomyr Taras Romankiw

Inventor： Peter A. Gruber ,  Frederic Maurer ,  Lubomyr Taras Romankiw

IPC: B23K3102

CPC classification number: H05K3/4069 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/246 ,  H05K3/4602 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09572 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0126 ,  H05K2203/085 ,  H01L2924/00

Abstract: An apparatus and a method for filling high aspect ratio holes in electronic substrates that can be advantageously used for filling holes having aspect ratios larger than 5:1 are disclosed. In the apparatus, a filler plate and a vacuum plate are used in conjunction with a connection means such that a gap is formed between the two plates to accommodate an electronic substrate equipped with high aspect ratio via holes. The filler plate is equipped with an injection slot while the vacuum plate is equipped with a vacuum slot such that when a substrate is sandwiched therein, via holes can be evacuated of air and injected with a liquid simultaneously from a bottom side and a top side of the substrate. The present invention novel apparatus and method allows the filling of via holes that have small diameters, i.e., as small as 10 &mgr;m, and high aspect ratios, i.e., at least 5:1 to be filled with an electrically conductive material such as a solder or a conductive polymer such that vias or interconnects can be formed in electronic substrates. The present invention apparatus and method can be advantageously used in fabricating substrates for display panels by forming conductive vias and interconnects for placing a voltage potential on pixel display elements formed on the display panels.

Abstract translation: 公开了一种用于填充电子基板中的高纵横比孔的装置和方法，其可以有利地用于填充具有大于5:1的纵横比的孔。 在装置中，填充板和真空板与连接装置结合使用，使得在两个板之间形成间隙以容纳配备有高纵横比通孔的电子基板。 填充板配备有注入槽，而真空板配备有真空槽，使得当基板夹在其中时，通孔可以从空气排出并同时从液体的底侧和顶侧注入液体 底物。 本发明的新型设备和方法允许填充具有小直径，即小至10um，高纵横比（即至少5:1）的通孔，以填充诸如焊料的导电材料 或导电聚合物，使得可以在电子基板中形成通孔或互连。 本发明的装置和方法可以有利地用于制造用于显示面板的基板，通过形成用于在形成在显示面板上的像素显示元件上放置电压电位的导电通孔和互连。

公开(公告)号：US06671949B2

公开(公告)日：2004-01-06

申请号：US09808086

申请日：2001-03-13

Applicant: Hirokazu Yoshioka ,  Norio Yoshida ,  Kenichiro Tanaka

Inventor： Hirokazu Yoshioka ,  Norio Yoshida ,  Kenichiro Tanaka

IPC: H01K310

CPC classification number: H05K3/4652 ,  H05K1/116 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/0055 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0969 ,  H05K2201/098 ,  H05K2201/09863 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/0796 ,  H05K2203/095 ,  H05K2203/1383 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T29/49165

Abstract: A multilayer printed wiring board is formed with a plurality of conductor layers laminated as a whole with insulating layers interposed, a non-penetrating via hole provided in the insulating layer as bottomed by the conductor layer exposed, a plated layer provided inside the via hole for electric connection between the conductor layers, the via hole being formed to be of a concave curved surface of a radius in a range of 20 to 100 &mgr;m in axially sectioned view at continuing zone of inner periphery to bottom surface of the via hole, whereby the equipotential surfaces occurring upon plating the plated layer are curved along the continuing zone to unify the density of current for rendering the plated layer uniform in the thickness without being thinned at the continuing zone.

Abstract translation: 多层印刷电路板形成有多个导体层，绝缘层整体层叠在一起，绝缘层中设置的非穿透通孔由导体层露出的底部，设置在通孔内部的镀层， 所述导体层之间的电连接，所述通孔形成为在通孔的内周到底面的连续区域的半径在20至100μm的范围内的轴向剖视图中的凹曲面的通孔，由此 在电镀镀层时发生的等电势面沿着连续区域弯曲，以统一电流密度，以使电镀层在厚​​度上均匀，而不会在连续区域变薄。

公开(公告)号：US06590165B1

公开(公告)日：2003-07-08

申请号：US09341792

申请日：1999-07-19

Applicant: Masaru Takada ,  Kiyotaka Tsukada ,  Hiroyuki Kobayashi ,  Hisashi Minoura ,  Yoshikazu Ukai ,  Mitsuhiro Kondo

Inventor： Masaru Takada ,  Kiyotaka Tsukada ,  Hiroyuki Kobayashi ,  Hisashi Minoura ,  Yoshikazu Ukai ,  Mitsuhiro Kondo

IPC: H05K111

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: In the production of a printed wiring board comprising innerlayer conductor circuits 161, 131 arranged among insulating layers 101˜103 and blind via-holes 141, 142 formed from an outermost surface of the insulating layer toward the innerlayer conductor circuit, an opening hole 160 is previously formed in a central portion of the innerlayer conductor circuit 161 located at the bottom of the blind via-hole 141, and laser beams are irradiated from the outermost surface of the insulating layer to form the blind via-holes 141, 142. Thereafter, a metal plated film is formed on surfaces of the innerlayer conductor circuits 13, 161 and the blind via-holes 141, 142.

Abstract translation: 在制造布置在绝缘层101〜103中的内层导体电路161,131和从绝缘层的最外表面向内层导体电路形成的盲通孔141,142的印刷电路板的情况下，开孔160为 预先形成在位于盲孔通孔141的底部的内层导体电路161的中心部分，并且从绝缘层的最外表面照射激光束以形成盲通孔141,142。 在内层导体电路13,161和盲孔通路141,142的表面上形成金属镀膜。

公开(公告)号：US06492600B1

公开(公告)日：2002-12-10

申请号：US09340758

申请日：1999-06-28

Applicant: Miguel A. Jimarez ,  Ross W. Keesler ,  Voya R. Markovich ,  Rajinder S. Rai ,  Cheryl L. Tytran-Palomaki

Inventor： Miguel A. Jimarez ,  Ross W. Keesler ,  Voya R. Markovich ,  Rajinder S. Rai ,  Cheryl L. Tytran-Palomaki

IPC: H05K109

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/3484 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09863 ,  H05K2203/043 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A chip carrier structure and method for forming the same having a receptor pad formed therein. The structure comprises a circuitized substrate having a conductive element on the surface, an External Dielectric Layer mounted on the circuitized substrate with an opening positioned above the conductive element to form a microvia. The walls of the microvia are first treated to enhance copper adhesion and then are electroplated to provide a receptor pad. Finally, a solder paste is deposited within the microvia to create a solder deposit or bump.

Abstract translation: 一种用于形成其中形成有受体垫的芯片载体结构和方法。 该结构包括在表面上具有导电元件的电路化基板，安装在电路化基板上的外部电介质层，其中开口位于导电元件上方以形成微孔。 首先处理微孔的壁以增强铜的粘附性，然后电镀以提供受体垫。 最后，在微孔内沉积焊膏以产生焊料沉积物或凸块。

公开(公告)号：US06461136B1

公开(公告)日：2002-10-08

申请号：US09383325

申请日：1999-08-26

Applicant: Peter A. Gruber ,  Frederic Maurer ,  Lubomyr Taras Romankiw

Inventor： Peter A. Gruber ,  Frederic Maurer ,  Lubomyr Taras Romankiw

IPC: H05K310

CPC classification number: H05K3/4069 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/246 ,  H05K3/4602 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09572 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0126 ,  H05K2203/085 ,  H01L2924/00

Abstract: An apparatus and a method for filling high aspect ratio holes in electronic substrates that can be advantageously used for filling holes having aspect ratios larger than 5:1 are disclosed. In the apparatus, a filler plate and a vacuum plate are used in conjunction with a connection means such that a gap is formed between the two plates to accommodate an electronic substrate equipped with high aspect ratio via holes. The filler plate is equipped with an injection slot while the vacuum plate is equipped with a vacuum slot such that when a substrate is sandwiched therein, via holes can be evacuated of air and injected with a liquid simultaneously from a bottom side and a top side of the substrate. The present invention novel apparatus and method allows the filling of via holes that have small diameters, i.e., as small as 10 &mgr;m, and high aspect ratios, i.e., at least 5:1 to be filled with an electrically conductive material such as a solder or a conductive polymer such that vias or interconnects can be formed in electronic substrates. The present invention apparatus and method can be advantageously used in fabricating substrates for display panels by forming conductive vias and interconnects for placing a voltage potential on pixel display elements formed on the display panels.

Abstract translation: 公开了一种用于填充电子基板中的高纵横比孔的装置和方法，其可以有利地用于填充具有大于5:1的纵横比的孔。 在装置中，填充板和真空板与连接装置结合使用，使得在两个板之间形成间隙以容纳配备有高纵横比通孔的电子基板。 填充板配备有注入槽，而真空板配备有真空槽，使得当基板夹在其中时，通孔可以从空气排出并同时从液体的底侧和顶侧注入液体 底物。 本发明的新型设备和方法允许填充具有小直径，即小至10um，高纵横比（即至少5:1）的通孔，以填充诸如焊料的导电材料 或导电聚合物，使得可以在电子基板中形成通孔或互连。 本发明的装置和方法可以有利地用于制造用于显示面板的基板，通过形成用于在形成在显示面板上的像素显示元件上放置电压电位的导电通孔和互连。

公开(公告)号：US20020004982A1

公开(公告)日：2002-01-17

申请号：US09358365

申请日：1999-07-21

Inventor： TAKAYUKI HAZE ,  TSUNEO YABUUCHI

IPC: H05K003/02 ,  H05K003/10

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0035 ,  H05K3/385 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/086 ,  H05K2203/087 ,  H05K2203/1157 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49165

Abstract: The method for producing a printed wiring board comprising the steps of preparing a conductive substrate, forming an insulating layer on one surface of the said substrate, forming at least one via hole in the insulating layer, thermally curing the insulating layer, and reducing at least one oxidized layer formed on the other conductive surface of the substrate during the curing operation. Alternatively, the thermal cure may be accomplished in an atmosphere (e.g., reducing gas, inactive gas, or mixtures thereof) not conducive to oxide formation on metallized circuit surfaces.

Abstract translation: 一种制造印刷电路板的方法，包括以下步骤：制备导电基板，在所述基板的一个表面上形成绝缘层，在绝缘层中形成至少一个通孔，热固化绝缘层，并至少减少 在固化操作期间在基板的另一导电表面上形成一个氧化层。 或者，热固化可以在不利于金属化电路表面上的氧化物形成的气氛（例如还原气体，惰性气体或其混合物）中完成。