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    Multicomponent integrated circuit package
    93.
    发明授权
    Multicomponent integrated circuit package 失效
    多组件集成电路封装

    公开(公告)号：US5220489A

    公开(公告)日：1993-06-15

    申请号：US774921

    申请日：1991-10-11

    Applicant: Joaquin Barreto ,  Juan O. Alfonso ,  Frank J. Juskey

    Inventor： Joaquin Barreto ,  Juan O. Alfonso ,  Frank J. Juskey

    IPC: H01L23/31 ,  H01L23/64 ,  H05K1/02

    CPC classification number: H05K1/0231 ,  H01L23/3121 ,  H01L23/642 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K2201/1053 ,  H05K2201/10689

    Abstract: An electronic package, comprising a circuit carrying substrate (30) and a semiconductor device (35). The substrate (30) has two opposing surfaces, the first or bottom surface having a plurality of solder pads (31) and the second or top surface having a circuitry pattern defined on it. A semiconductor device (35) is attached to the top surface of the circuit carrying substrate (30). A molded body (33) is formed completely around the semiconductor device (35) in order to encapsulate it, the molded body also substantially covering the top surface of the circuit carrying substrate (30). A layer of metal deposited directly on the molded body and the top surface of the circuit carrying substrate is delineated into another conductive circuitry pattern (38), with part of the pattern (36) connected to the circuitry pattern on the circuit carrying substrate. An electronic component (32) is mounted on the molded body (33) and electrically connected to the conductive circuitry pattern (38).

    Abstract translation: 一种电子封装，包括电路承载衬底（30）和半导体器件（35）。 衬底（30）具有两个相对的表面，第一或下表面具有多个焊盘（31），并且第二或顶部表面具有限定在其上的电路图案。 半导体器件（35）附接到电路承载衬底（30）的顶表面。 模制体（33）完全围绕半导体器件（35）形成以封装，成型体也基本覆盖电路承载衬底（30）的顶表面。 将直接沉积在成型体上的金属层和电路承载衬底的顶表面描绘成另一个导电电路图案（38），其中一部分图案（36）连接到电路承载衬底上的电路图案。 电子部件（32）安装在成型体（33）上并电连接到导电电路图案（38）。

    Method of building a variety of complex high performance IC devices
    94.
    发明授权
    Method of building a variety of complex high performance IC devices 失效
    构建各种复杂高性能IC器件的方法

    公开(公告)号：US4955131A

    公开(公告)日：1990-09-11

    申请号：US358316

    申请日：1989-05-30

    Applicant: Louis Edmond Chall, Jr.

    Inventor： Louis Edmond Chall, Jr.

    IPC: G01R31/3185 ,  G11C29/00 ,  H01L23/13 ,  H01L23/473 ,  H01L23/52 ,  H01L23/538 ,  H05K1/00 ,  H05K1/14 ,  H05K3/34 ,  H05K3/40 ,  H05K7/20

    CPC classification number: H01L23/52 ,  G01R31/318505 ,  G11C29/006 ,  H01L23/13 ,  H01L23/473 ,  H01L23/5385 ,  H05K3/3442 ,  H05K7/20545 ,  H01L2924/0002 ,  H01L2924/15162 ,  H01L2924/3011 ,  H05K1/0286 ,  H05K1/142 ,  H05K2201/09181 ,  H05K2201/09418 ,  H05K2201/1053 ,  H05K2201/10727 ,  H05K3/403 ,  Y02P70/613 ,  Y10T29/49117 ,  Y10T29/49126

    Abstract: A novel packaging system for VLSI circuits allows low-cost construction and maintenance of complex high density high-performance devices with low power requirements. The devices can be individually created by software means from a small selection of standardizable IC chips by disposing a plurality of chips in leadless chip carriers in a mosaic on a substrate, and configuring them by software to selectively communicate with other chips of the mosaic or even to individually change their operating function. The immediate juxtaposition of the chip carriers in the mosaic eliminates transmission line data skew, and also allows considerable savings in chip space and power requirements by dispensing with interconnection drivers, receivers and bonding pads. The chip carrier mosaics may be assembled into modules suitable for plug-in connection to an interconnecting backplane to create even larger devices, and individual modules can be dynamically tested in their high-performance mode by configuring one or more modules as test modules and either plugging them into modules to be tested or making them a permanent part of the device's module array.

    Abstract translation: 用于VLSI电路的新型封装系统允许低成本构建和维护具有低功耗要求的复杂高密度高性能器件。 这些设备可以通过软件方式从小型可标准化的IC芯片中单独创建，通过在基板上的马赛克中的无引线芯片载体中布置多个芯片，并且通过软件来配置它们以选择性地与马赛克的其他芯片进行通信 单独改变其操作功能。 芯片载体在马赛克中的并行排列消除了传输线数据偏移，并且还通过分配互连驱动器，接收器和接合焊盘来大大节省芯片空间和功率需求。 芯片载体马赛克可以组装成适合于插入连接到互连背板的模块，以创建更大的设备，并且可以通过将一个或多个模块配置为测试模块和插件来以高性能模式动态测试各个模块 它们被组合成要测试的模块或使其成为设备模块阵列的永久部分。

    Component module for piggyback mounting on a circuit package having dual-in-line leads, and methods of fabricating same
    97.
    发明授权
    Component module for piggyback mounting on a circuit package having dual-in-line leads, and methods of fabricating same 失效
    用于搭载在具有双列直线引线的电路封装上的组件模块及其制造方法

    公开(公告)号：US4617708A

    公开(公告)日：1986-10-21

    申请号：US704700

    申请日：1985-04-02

    Applicant: William J. Fanning

    Inventor： William J. Fanning

    IPC: H01L23/495 ,  H01L23/552 ,  H01L25/10 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34 ,  H05K7/10 ,  H05K7/20 ,  H05K9/00 ,  H01G7/00

    CPC classification number: H05K9/00 ,  H01L23/49589 ,  H01L23/552 ,  H01L25/105 ,  H05K1/18 ,  H05K7/1092 ,  H01L2225/1029 ,  H01L2225/1094 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K2201/10015 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10689 ,  H05K2201/10984 ,  H05K2203/0415 ,  H05K3/3447 ,  Y10T29/435 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49142 ,  Y10T29/49172

    Abstract: A component module (15, 70), adapted for piggyback mounting on an IC Dip (51,81), preferably incorporates a decoupling capacitor (18, 44, 74), with opposite end electrodes (23, 24), encapsulated within a molded housing (21, 72) of preferably parallelepiped configuration. The electrodes are uniquely connected to only two of preferably four rectangularly shaped terminals (26-29, 76-79) that project downwardly from different corners of the housing. The terminals, as well as an optional heat sink (61) are preferably formed out of a strip stock carrier (33). The two capacitor-connected terminals (27, 29 and 77, 79) are uniquely diagonally disposed and spaced, for a decoupling application, so as to respectively engage the battery and ground leads of a standard pin-out DIP (51, 81). The other two diagonally disposed component module terminals (26, 28 or 76, 78) are electrically isolated from the capacitor, being employed only to facilitate the mounting of the module on an associated DIP. In one component module embodiment (15, FIG. 1), the terminals (26-29) are adapted for soldered securement to a circuit board (54), whereas in a second embodiment (70, FIG. 6) the terminals (76-79) are adapted to be snap-locked on and, thereafter, soldered to, upper horizontal shoulder portion (82a) of respectively aligned leads (82) of a supporting DIP (81).

    Abstract translation: 组件模块（15,70）适于背负式安装在IC浸入（51,81）上，优选地包含一个去耦电容器（18,44,74），其具有相对的端电极（23,24），封装在模制 壳体（21,72）优选为平行六面体构型。 电极仅与两个优选地从壳体的不同角落向下突出的四个矩形端子（26-29,76-79）连接。 这些端子以及可选的散热器（61）优选地由带状载体（33）形成。 两个电容器连接的端子（27,29和77,79）独特地对角地设置和隔开，用于去耦应用，以便分别接合标准引脚DIP（51,81）的电池和接地引线。 另外两个对角布置的部件模块端子（26,28或76,78）与电容器电隔离，仅用于便于将模块安装在相关联的DIP上。 在一个组件模块实施例（图1中的15）中，端子（26-29）适于焊接固定到电路板（54），而在第二实施例（70，图6）中， 79）适于在支撑DIP（81）的分别对准的引线（82）的上部水平肩部（82a）上被卡扣锁定，然后被焊接到其上。

    Method of manufacturing an electrical circuit wiring arrangement
    98.
    发明授权
    Method of manufacturing an electrical circuit wiring arrangement 失效
    制造电路布线装置的方法

    公开(公告)号：US4486817A

    公开(公告)日：1984-12-04

    申请号：US409514

    申请日：1982-08-19

    Applicant: Kazuaki Matsumura ,  Seiki Nakanishi

    Inventor： Kazuaki Matsumura ,  Seiki Nakanishi

    IPC: H05K7/02 ,  H05K3/34 ,  H05K7/00 ,  H05K7/04

    CPC classification number: H05K3/34 ,  H05K7/005 ,  H05K2201/10401 ,  H05K2201/10424 ,  H05K2201/1053 ,  H05K2201/10962 ,  H05K3/3468 ,  Y10T29/4913 ,  Y10T29/49144

    Abstract: A method of manufacturing an electrical circuit wiring assembly comprises the steps of preparing a first sub-assembly having a metal board chassis and a first circuit element provided with hard stiff leads, preparing a second sub-assembly having a second circuit element provided with soft thin leads and an eyelet terminal for connecting the soft thin lead to the hard lead by means of a soldered junction, and assembling the first and second sub-assemblies by a soldering operating to form a main wiring assembly. In the second sub-assembly the second circuit element and the eyelet terminal are carried temporarily on an unsolderable mounting tool. The first and second sub-assemblies are temporarily coupled to each other during the forming of the main assembly by means of a coupling tool or jig for applying molten solder to an exposed connecting portion of the eyelet terminal and to portions of the hard and soft leads extending from the eyelet terminal. After soldering, the unsolderable mounting tool and the coupling tool are removed from the soldered main wiring assembly so that a three-dimensional wiring assembly is obtained.

    Abstract translation: 一种制造电路布线组件的方法包括以下步骤：制备具有金属板底座的第一子组件和设置有硬刚性导线的第一电路元件，制备具有第二电路元件的第二子组件，该第二电路元件设置有软薄片 引线和用于通过焊接接头将软薄导线连接到硬引线的孔眼端子，以及通过焊接操作组装第一和第二子组件以形成主布线组件。 在第二子组件中，第二电路元件和孔眼端子临时携带在不可焊接的安装工具上。 第一和第二子组件在通过用于将熔融焊料施加到孔眼端子的暴露的连接部分的连接工具或夹具以及硬和软引线的部分处，在主组件形成期间暂时彼此耦合 从孔眼终端延伸。 在焊接之后，将不可焊接的安装工具和联接工具从焊接的主配线组件移除，从而获得三维接线组件。

    Electrical circuit wiring arrangement and its soldering method
    99.
    发明授权
    Electrical circuit wiring arrangement and its soldering method 失效
    电路布线及其焊接方法

    公开(公告)号：US4373260A

    公开(公告)日：1983-02-15

    申请号：US175960

    申请日：1980-08-07

    Applicant: Kazuaki Matsumura ,  Seiki Nakanishi

    Inventor： Kazuaki Matsumura ,  Seiki Nakanishi

    IPC: H05K7/02 ,  H05K3/34 ,  H05K7/00 ,  H05K7/04

    CPC classification number: H05K3/34 ,  H05K7/005 ,  H05K2201/10401 ,  H05K2201/10424 ,  H05K2201/1053 ,  H05K2201/10962 ,  H05K3/3468 ,  Y10T29/4913 ,  Y10T29/49144

    Abstract: A method of manufacturing an electrical circuit wiring assembly comprises the steps of preparing a first sub-assembly having a metal board chassis and a first circuit element provided with hard stiff leads, preparing a second sub-assembly having a second circuit element provided with soft thin leads and an eyelet terminal for connecting the soft thin lead to the hard lead by means of a soldered junction, and assembling the first and second sub-assemblies by a soldering operation to form a main wiring assembly. In the second sub-assembly the second circuit element and the eyelet terminal are carried temporarily on an unsolderable mounting tool. The first and second sub-assemblies are temporarily coupled to each other during the forming of the main assembly by means of a coupling tool or jig for applying molten solder to an exposed connecting portion of the eyelet terminal and to portions of the hard and soft leads extending from the eyelet terminal. After soldering, the unsolderable mounting tool and the coupling tool are removed from the soldered main wiring assembly so that a three-dimensional wiring assembly is obtained.

    Abstract translation: 一种制造电路布线组件的方法包括以下步骤：制备具有金属板底座的第一子组件和设置有硬刚性导线的第一电路元件，制备具有第二电路元件的第二子组件，该第二电路元件设置有软薄片 引线和用于通过焊接接头将软薄导线连接到硬引线的孔眼端子，以及通过焊接操作组装第一和第二子组件以形成主布线组件。 在第二子组件中，第二电路元件和孔眼端子临时携带在不可焊接的安装工具上。 第一和第二子组件在通过用于将熔融焊料施加到孔眼端子的暴露的连接部分的耦合工具或夹具以及硬和软引线的部分处，在主组件形成期间暂时彼此耦合 从孔眼终端延伸。 在焊接之后，将不可焊接的安装工具和联接工具从焊接的主配线组件移除，从而获得三维接线组件。

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