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    Sealed light emitting diode assemblies including annular gaskets and methods of making same
    91.
    发明申请
    Sealed light emitting diode assemblies including annular gaskets and methods of making same 失效
    密封发光二极管组件，包括环形垫片及其制造方法

    公开(公告)号：US20080220549A1

    公开(公告)日：2008-09-11

    申请号：US11715746

    申请日：2007-03-08

    Applicant: Jeffrey Nall ,  Babi Koushik Saha ,  Bill Xin Wang

    Inventor： Jeffrey Nall ,  Babi Koushik Saha ,  Bill Xin Wang

    IPC: H01J40/14

    CPC classification number: H05K3/284 ,  F21K9/00 ,  F21V31/005 ,  F21V31/04 ,  F21Y2115/10 ,  H05K2201/0989 ,  H05K2201/10106 ,  H05K2201/2018 ,  H05K2203/1316

    Abstract: An optoelectronic device assembly includes a circuit board and an optoelectronic device disposed on the circuit board and electrically connected with the circuit board. An annular gasket is disposed on the circuit board and surrounds the optoelectronic device. A sealant is disposed over and seals at least a portion of the circuit board and also covers at least an outer annular portion of the annular gasket. The sealant is not disposed over the optoelectronic device. In a method, an optoelectronic device is disposed on a circuit board, the disposing including electrically connecting the optoelectronic device with the circuit board. An annular gasket is disposed on the circuit board to surround the optoelectronic device. The circuit board is sealed with a sealant that also covers at least an outer annular portion of the annular gasket, but does not cover the optoelectronic device.

    Abstract translation: 光电子器件组件包括电路板和设置在电路板上并与电路板电连接的光电器件。 环形垫片设置在电路板上并围绕光电器件。 将密封剂设置在并且密封电路板的至少一部分并且还覆盖环形垫圈的至少外部环形部分。 密封剂未设置在光电子器件上。 在一种方法中，光电子器件设置在电路板上，该布置包括将光电器件与电路板电连接。 环形垫圈设置在电路板上以围绕光电子器件。 电路板用密封剂密封，密封剂还覆盖环形垫片的至少外环形部分，但不覆盖光电子器件。

    STACKED MOUNTING STRUCTURE
    92.
    发明申请
    STACKED MOUNTING STRUCTURE 有权
    堆叠安装结构

    公开(公告)号：US20080170376A1

    公开(公告)日：2008-07-17

    申请号：US12015212

    申请日：2008-01-16

    Applicant: Takanori Sekido

    Inventor： Takanori Sekido

    IPC: H05K7/00

    CPC classification number: H05K3/368 ,  H01L2924/0002 ,  H05K1/144 ,  H05K3/321 ,  H05K2201/0367 ,  H05K2201/09181 ,  H05K2201/10378 ,  H05K2201/2018 ,  H01L2924/00

    Abstract: In a stacked mounting structure At least a pair of a first connecting terminal and a second connecting terminal is formed, and further, the stacked mounting structure includes a protruding electrode which is provided on at least any one of the first connecting terminal and the second connecting terminal, and an electroconductive paste which is formed on a side surface of an intermediate substrate, and which electrically connects the first connecting terminal and the second connecting terminal. The first connecting terminal and the second connecting terminal are exposed by a recess in a surface of the intermediate substrate. The first connecting terminal and the second connecting terminal are electrically connected via the protruding electrode and the electroconductive paste in the recess which is provided in the intermediate substrate.

    Abstract translation: 在堆叠安装结构中，形成至少一对第一连接端子和第二连接端子，此外，堆叠的安装结构包括设置在第一连接端子和第二连接端子中的至少任一个上的突出电极 端子，以及形成在中间基板的侧面上并将第一连接端子和第二连接端子电连接的导电性糊料。 第一连接端子和第二连接端子由中间基板的表面中的凹部露出。 第一连接端子和第二连接端子经由设置在中间基板的凹部中的突出电极和导电浆料电连接。

    Laminated bond of multilayer circuit board having embedded chips
    93.
    发明申请
    Laminated bond of multilayer circuit board having embedded chips 失效
    具有嵌入式芯片的多层电路板的叠层结合

    公开(公告)号：US20080101044A1

    公开(公告)日：2008-05-01

    申请号：US11589889

    申请日：2006-10-31

    Applicant: Roger Chang

    Inventor： Roger Chang

    IPC: H05K1/18

    CPC classification number: H05K1/186 ,  H01L23/5389 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/112 ,  H05K3/28 ,  H05K3/4623 ,  H05K2201/10674 ,  H05K2201/2018 ,  H05K2203/049 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A multilayer circuit board has a bottom and an upper multilayer circuit boards, a glue layer, multiple outer contact vias and two insulating lacquer layers. The bottom and the upper multilayer circuit boards respectively have multiple conductive wires, an insulating layer, a frame, multiple chips, a press laminate, a patterned conductive layer and at least one inner contact via. The glue layer sticks the bottom and the upper multilayer circuit boards together. The multiple contact vias are formed through the bottom and the upper multilayer circuit boards to electronically interconnect the conductive wires and the patterned conductive layers in the bottom and the upper multilayer circuit boards. The insulating lacquer layers are respectively coated under and on portions of the patterned conductive layers in the bottom and the upper multilayer circuit boards to protect the patterned conductive layers, wherein the un-coated patterned conductive layers become multiple contacts.

    Abstract translation: 多层电路板具有底部和上部多层电路板，胶层，多个外部接触通孔和两个绝缘漆层。 底部和上部多层电路板分别具有多根导电线，绝缘层，框架，多个芯片，压制叠层，图案化导电层和至少一个内部接触通孔。 胶层将底部和上层多层电路板粘在一起。 多个接触孔通过底部和上部多层电路板形成，以电连接导电线和底部和上部多层电路板中的图案化导电层。 绝缘漆层分别涂覆在底部和上部多层电路板中的图案化导电层的部分之下和之上，以保护图案化的导电层，其中未涂覆的图案化导电层变成多个接触。

    High Capacity Thin Module System and Method
    94.
    发明申请
    High Capacity Thin Module System and Method 有权
    高容量薄模块系统和方法

    公开(公告)号：US20080030966A1

    公开(公告)日：2008-02-07

    申请号：US11869644

    申请日：2007-10-09

    Applicant: Paul Goodwin

    Inventor： Paul Goodwin

    IPC: H05K7/06

    CPC classification number: G11C5/04 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/118 ,  H05K1/181 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2203/1572 ,  H01L2224/0401

    Abstract: Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile. The flexible circuit may exhibit one or two more conductive layers, and may have changes in the layered structure of have split layers. Other embodiments may stagger or offset the ICs or include greater numbers of ICs.

    Abstract translation: 多个DIMM电路或实例被呈现在单个模块中。 在一些实施例中，存储器集成电路（优选CSP）和伴随的AMB或伴随的存储器寄存器被布置在柔性电路的每一侧的两个场中的两个等级中。 柔性电路具有沿着一侧设置的扩展触点。 柔性电路围绕支撑衬底或板设置，以在构造的模块的每一侧上放置一个完整的DIMM电路或实例化。 在替代但也优选的实施例中，最靠近基板的柔性电路一侧的IC至少部分地设置在优选实施例中在基板中的窗口，凹穴或切口区域中。 其他实施例可以仅填充柔性电路的一侧，或者可以仅移除足够的衬底材料以减少但不消除整个衬底对整体轮廓的贡献。 柔性电路可以表现出一个或两个更多的导电层，并且可以具有分层的层状结构的变化。 其他实施例可能错开或偏移IC或包括更多数量的IC。

    High capacity thin module system and method
    95.
    发明授权
    High capacity thin module system and method 失效
    大容量薄模块系统及方法

    公开(公告)号：US07324352B2

    公开(公告)日：2008-01-29

    申请号：US11068688

    申请日：2005-03-01

    Applicant: Paul Goodwin

    Inventor： Paul Goodwin

    IPC: H05K1/11

    CPC classification number: G11C5/04 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/118 ,  H05K1/181 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2203/1572 ,  H01L2224/0401

    Abstract: Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers. Other embodiments may stagger or offset the ICs or include greater numbers of ICs.

    Abstract translation: 多个DIMM电路或实例被呈现在单个模块中。 在一些实施例中，存储器集成电路（优选CSP）和伴随的AMB或伴随的存储器寄存器被布置在柔性电路的每一侧的两个场中的两个等级中。 柔性电路具有沿着一侧设置的扩展触点。 柔性电路围绕支撑衬底或板设置，以在构造的模块的每一侧上放置一个完整的DIMM电路或实例化。 在替代但也优选的实施例中，最靠近基板的柔性电路一侧的IC至少部分地设置在优选实施例中在基板中的窗口，凹穴或切口区域中。 其他实施例可以仅填充柔性电路的一侧，或者可以仅移除足够的衬底材料以减少但不消除整个衬底对整体轮廓的贡献。 柔性电路可以表现出一个或两个或更多个导电层，并且可以具有分层结构的变化或具有分裂层。 其他实施例可能错开或偏移IC或包括更多数量的IC。

    Carrier structure stacking system and method
    96.
    发明申请
    Carrier structure stacking system and method 有权
    载体结构堆垛系统及方法

    公开(公告)号：US20070290312A1

    公开(公告)日：2007-12-20

    申请号：US11452531

    申请日：2006-06-14

    Applicant: Julian Partridge

    Inventor： Julian Partridge

    IPC: H01L23/02

    CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K3/429 ,  H05K2201/09481 ,  H05K2201/0959 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/2018 ,  H01L2924/00

    Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits.

    Abstract translation: 本发明提供了一种系统和方法，用于选择性地堆叠和互连带引线的封装集成电路器件，其具有上IC的引线的脚与下IC的引线的上肩之间的连接，而实现堆叠相关的堆叠内的导电性转换 组成IC之间的连接在沿着堆叠的引导侧定向的多层插入件或载体结构中实现，其中选定的导电转移与其它选定的导电转换电互连。

    ENCAPSULATED MULTI-PHASE ELECTRONICS HEAT SINK
    97.
    发明申请
    ENCAPSULATED MULTI-PHASE ELECTRONICS HEAT SINK 有权
    封装多相电子散热器

    公开(公告)号：US20070285892A1

    公开(公告)日：2007-12-13

    申请号：US11422730

    申请日：2006-06-07

    Applicant: Eric S. Mindock ,  John R. Scott

    Inventor： Eric S. Mindock ,  John R. Scott

    IPC: H05K7/20

    CPC classification number: H05K1/0203 ,  H01L23/427 ,  H01L2924/0002 ,  H05K2201/064 ,  H05K2201/10371 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2203/083 ,  H01L2924/00

    Abstract: An apparatus and method for cooling electronics is disclosed. An encapsulated inert non-conductive fluid is used to transfer heat directly from an electrical circuit including a die on a substrate to an external heatsink. The top of a flip chip die (e.g. a ceramic column grid array flip chip) may be enclosed with a metallic cover. The metallic cover is sealed to an outer frame, which in turn is sealed to metallization on the top of the flip chip through a flexure, minimizing mechanical load imparted to the flip chip. This forms a hermetic cavity enclosing the die. This hermetic cavity is partially filled with an inert non conductive fluid, which vaporizes when heated. Condensation occurs on the inner surface of the metal cover where the heat may be conducted into the outer frame for removal (e.g. rejection from the spacecraft).

    Abstract translation: 公开了一种用于冷却电子设备的装置和方法。 使用封装的惰性非导电流体将热量直接从包括基板上的管芯的电路传递到外部散热器。 倒装晶片管芯的顶部（例如，陶瓷柱栅格阵列倒装芯片）可以用金属盖封装。 金属盖被密封到外框架上，外框架通过挠曲件而被密封到倒装芯片的顶部上的金属化，从而使施加到倒装芯片的机械载荷最小化。 这形成封闭模具的密封腔。 该密封腔部分地填充有惰性非导电流体，其在加热时蒸发。 在金属盖的内表面上发生冷凝，其中热量可以传导到外框架中以便移除（例如从航天器排出）。

    Thin multichip flex-module
    100.
    发明申请
    Thin multichip flex-module 有权
    薄多芯片柔性模块

    公开(公告)号：US20070211426A1

    公开(公告)日：2007-09-13

    申请号：US11715205

    申请日：2007-03-07

    Applicant: James E. Clayton ,  Zakaryae Fathi

    Inventor： James E. Clayton ,  Zakaryae Fathi

    IPC: H05K7/20

    CPC classification number: H05K1/189 ,  H01L23/473 ,  H01L23/5387 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K3/0061 ,  H05K3/0064 ,  H05K2201/056 ,  H05K2201/064 ,  H05K2201/09445 ,  H05K2201/2018 ,  H01L2924/00

    Abstract: A multichip module comprises: a first rigid member defining one outer wall of a chamber; a second rigid member defining the opposite wall of the chamber; a sealable interface joining the first and second rigid members at their peripheries, whereby a hollow chamber is formed; a flex circuit having a plurality of integrated circuit chips disposed thereon, the flex circuit affixed to at least one of the first and second rigid members; electrical contacts at least partially extending outward through the sealable interface; and, a fluid inlet and a fluid outlet configured to permit fluid to flow through the chamber whereby heat generated by the integrated circuit chips may be removed from the module.

    Abstract translation: 多芯片模块包括：限定室的一个外壁的第一刚性构件; 限定所述腔室的相对壁的第二刚性构件; 可密封的界面，在其周边处连接第一和第二刚性构件，由此形成中空室; 具有设置在其上的多个集成电路芯片的柔性电路，所述柔性电路固定到所述第一和第二刚性构件中的至少一个; 至少部分地通过可密封界面向外延伸的电触点; 以及流体入口和流体出口，其构造成允许流体流过所述室，由此可以从模块移除由集成电路芯片产生的热量。

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