公开(公告)号：US11837554B2

公开(公告)日：2023-12-05

申请号：US17200411

申请日：2021-03-12

Applicant: Kioxia Corporation

Inventor： Ryujiro Bando ,  Hitoshi Ikei

IPC: H01L23/552 ,  H05K1/03 ,  H01L23/00 ,  H01L23/498 ,  H05K3/34 ,  H05K1/18 ,  H01L25/065

CPC classification number: H01L23/552 ,  H05K1/0306 ,  H01L23/49816 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06562 ,  H01L2924/14511 ,  H05K1/181 ,  H05K3/3494 ,  H05K2201/0112 ,  H05K2201/0175 ,  H05K2201/0989 ,  H05K2201/10159

Abstract: A semiconductor package of an embodiment includes a wiring substrate, a semiconductor chip provided on an upper surface of the wiring substrate, a sealing resin covering surfaces of the wiring substrate and the semiconductor chip, an infrared reflection layer containing any of aluminum, aluminum oxide, and titanium oxide, and an external terminal provided on a lower surface of the wiring substrate. The wiring substrate is electrically connectable with a printed wiring board through the external terminal. The infrared reflection layer is provided to the sealing resin on an upper side of a surface of the semiconductor chip on a side opposite to an upper surface of the wiring substrate.

公开(公告)号：US11778739B2

公开(公告)日：2023-10-03

申请号：US17188528

申请日：2021-03-01

Applicant: Polytronics Technology Corp.

Inventor： Kuo Hsun Chen ,  Cheng Tsung Yang ,  Feng-Chun Yu ,  Kai-Wei Lo

IPC: H05K1/05 ,  H01L23/373

CPC classification number: H05K1/053 ,  H01L23/3735 ,  H05K1/056 ,  H05K2201/0129 ,  H05K2201/0175 ,  H05K2201/0191 ,  H05K2201/0209 ,  Y10T428/12569

Abstract: A thermally conductive board includes a metal substrate, a metal layer, a thermal conductive insulating polymer layer, and a ceramic material layer. The thermal conductive insulating polymer layer is located between the metal layer and the metal substrate. The ceramic material layer includes an upper ceramic layer or a lower ceramic layer, or includes both the upper ceramic layer and the lower ceramic layer. The upper ceramic layer is disposed between the metal layer and the thermal conductive insulating polymer layer, and the lower ceramic layer is disposed between the thermal conductive insulating polymer layer and the metal substrate.

公开(公告)号：US11671690B2

公开(公告)日：2023-06-06

申请号：US17653985

申请日：2022-03-08

Applicant: LG INNOTEK CO., LTD.

Inventor： Jong Ho Chung ,  Sung Il Lee

IPC: H04N23/55 ,  G02B7/08 ,  G02B27/64 ,  H05K3/30 ,  H04N23/54 ,  G02B7/00 ,  G02B7/09 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K1/03

CPC classification number: H04N23/55 ,  G02B7/006 ,  G02B7/08 ,  G02B7/09 ,  G02B27/646 ,  H04N23/54 ,  H05K3/305 ,  H05K1/0281 ,  H05K1/0306 ,  H05K1/147 ,  H05K3/341 ,  H05K2201/0175 ,  H05K2201/09036 ,  H05K2201/10121 ,  H05K2201/10151

Abstract: A camera module of an embodiment may comprise: a first holder in which a filter is mounted; a lens barrel that is provided to be vertically movable in a first direction with respect to the first holder; a lens operating device that comprises a terminal and moves the lens barrel in the first direction; a first circuit board that is disposed under the first holder and on which an image sensor is mounted; a soldering portion for electrically connecting the terminal of the lens operating device to the first circuit board; and a coupling reinforcement portion that is disposed to face the soldering portion and couples the lens operating device and the first circuit board.

公开(公告)号：US09893008B2

公开(公告)日：2018-02-13

申请号：US15193355

申请日：2016-06-27

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Byron Williams ,  Shrinivasan Jaganathan ,  David Larkin ,  Dhaval Atul Saraiya

IPC: H05K1/09 ,  H01L23/522 ,  H05K1/03 ,  H05K1/16 ,  H01L23/62 ,  H05K1/02 ,  H05K3/46 ,  H05K3/00 ,  H05K1/11 ,  H01L23/498 ,  H01L23/528 ,  H01L23/532 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L23/49811 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/538 ,  H01L23/62 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/14335 ,  H05K1/0256 ,  H05K1/0257 ,  H05K1/0262 ,  H05K1/0306 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/112 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0088 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/0746 ,  H05K2201/09409 ,  H05K2201/0949 ,  H05K2201/09672 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

公开(公告)号：US20180014404A1

公开(公告)日：2018-01-11

申请号：US15273672

申请日：2016-09-22

Applicant: Unimicron Technology Corp.

Inventor： Yu-Chung HSIEH ,  Chun-Hsien CHIEN ,  Wei-Ti LIN ,  Yu-Hua CHEN

IPC: H05K1/03 ,  H05K1/02

CPC classification number: H05K1/0306 ,  H05K1/0271 ,  H05K3/0052 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/068 ,  H05K2201/09845

Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

公开(公告)号：US20180009141A1

公开(公告)日：2018-01-11

申请号：US15679146

申请日：2017-08-16

Applicant: NINGBO SUNNY OPOTECH CO., LTD.

Inventor： Mingzhu WANG ,  Bojie Zhao ,  Takehiko Tanaka ,  Nan Guo ,  Zhenyu Chen ,  Heng Jiang ,  Zhongyu Luan ,  Fengsheng Xi ,  Feifan Chen ,  Liang Ding

IPC: B29C45/14 ,  H04M1/02 ,  G02B7/02 ,  G02B7/00 ,  G02B5/20 ,  H04N5/225 ,  H01L27/146 ,  B29L31/34

CPC classification number: G02B7/021 ,  B29C45/14639 ,  B29L2031/3481 ,  G02B3/0075 ,  G02B5/201 ,  G02B7/006 ,  G02B13/001 ,  G02B13/004 ,  H01L21/565 ,  H01L25/0655 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1469 ,  H04M1/0264 ,  H04N5/2252 ,  H04N5/2253 ,  H04N5/2254 ,  H04N5/2257 ,  H04N5/2258 ,  H05K1/0203 ,  H05K1/0274 ,  H05K1/183 ,  H05K1/185 ,  H05K1/189 ,  H05K2201/0141 ,  H05K2201/0158 ,  H05K2201/0175 ,  H05K2201/09036 ,  H05K2201/10121

Abstract: An array imaging module includes a molded photosensitive assembly which includes a supporting member, at least a circuit board, at least two photosensitive units, at least two lead wires, and a mold sealer. The photosensitive units are coupled at the chip coupling area of the circuit board. The lead wires are electrically connected the photosensitive units at the chip coupling area of the circuit board. The mold sealer includes a main mold body and has two optical windows. When the main mold body is formed, the lead wires, the circuit board and the photosensitive units are sealed and molded by the main mold body of the mold sealer, such that after the main mold body is formed, the main mold body and at least a portion of the circuit board are integrally formed together at a position that the photosensitive units are aligned with the optical windows respectively.

公开(公告)号：US20170311446A1

公开(公告)日：2017-10-26

申请号：US15253615

申请日：2016-08-31

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS S.R.L.

Inventor： Simon DODD ,  Roberto BRIOSCHI

IPC: H05K1/18 ,  H05K1/03 ,  H05K3/10 ,  H05K3/40 ,  H05K1/11

CPC classification number: H05K1/181 ,  B81C1/0023 ,  H01L2924/1461 ,  H05K1/0272 ,  H05K1/0293 ,  H05K1/0306 ,  H05K1/111 ,  H05K3/10 ,  H05K3/4007 ,  H05K2201/0175 ,  H05K2201/0338 ,  H05K2201/0391 ,  H05K2201/09727 ,  H05K2201/09763 ,  H05K2201/09827 ,  H05K2201/10083 ,  H05K2201/10159 ,  H05K2201/10181 ,  H05K2203/171 ,  H05K2203/175

Abstract: The present disclosure is directed to a ceramic substrate that includes a plurality of contact pads, a plurality of electrical traces, and a microelectromechanical die. Contacts on the die are coupled to the plurality of contact pads through the plurality of electrical traces. The substrate also includes a plurality of memory bits formed directly on the substrate. Each memory bit is coupled between a first one of the contact pads and a second one of the contact pads.

公开(公告)号：US09674944B2

公开(公告)日：2017-06-06

申请号：US15157627

申请日：2016-05-18

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Byung-Moon Kim ,  Ho-Sik Park ,  Dong-Keun Lee ,  Sung-Jun Lee

IPC: H05K1/02 ,  H05K3/10 ,  H05K3/00 ,  H05K3/40 ,  H05K1/03 ,  H05K3/46

CPC classification number: H05K1/0271 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/0366 ,  H05K3/0011 ,  H05K3/0052 ,  H05K3/10 ,  H05K3/4038 ,  H05K3/429 ,  H05K3/4605 ,  H05K3/4611 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0195

Abstract: A printed circuit board and a method of manufacturing the same are provided. A printed circuit board having conductive patterns formed in multilayers on an insulating material laminated on both surfaces of a glass core is provided. The printed circuit board includes a first insulating material disposed on a first surface and a second surface of the glass core. and a second insulating material disposed on the first insulating material. The first insulating material surrounds a first portion of a side surface of the glass core and the second insulating material surrounds a second portion of the side surface of the glass core, the second portion being a portion of the glass core not surrounded by the first insulating material.

公开(公告)号：US09497837B2

公开(公告)日：2016-11-15

申请号：US14351682

申请日：2012-09-13

Applicant: Takahiro Fujimori ,  Shingo Suzuki ,  Kensaku Asakura

Inventor： Takahiro Fujimori ,  Shingo Suzuki ,  Kensaku Asakura

IPC: H05F3/00 ,  H05F3/04 ,  H01T4/12 ,  H01T1/24 ,  H05K1/02

CPC classification number: H05F3/04 ,  H01T1/24 ,  H01T4/12 ,  H05K1/026 ,  H05K2201/0175 ,  H05K2201/0209 ,  H05K2201/09272

Abstract: An electrostatic protection device with an improved durability with repeated use and an excellent discharging property is provided. The electrostatic protection device 100 comprising an insulating laminate 11, a pair of discharge electrodes 12 and 13 inside the insulating laminate 11 and a discharge triggered part 14 disposed between these discharge electrodes and at the periphery of the end portion of the discharge electrode is configured by disposing glass-containing insulating layers 15 and 16 on the surfaces of the discharge electrodes. The flow of conductive inorganic materials in the discharge electrodes towards the discharge triggered part caused by the discharging process can be inhibited by arranging the insulating layer containing glass on the surfaces of the discharge electrodes.

Abstract translation: 提供一种具有反复使用的改善的耐久性和优异的放电性的静电保护装置。 包括绝缘层压体11，绝缘叠层11内的一对放电电极12和13以及设置在这些放电电极之间的放电触发部分14和放电电极的端部周边的静电保护装置100由 在放电电极的表面上设置含玻璃的绝缘层15和16。 通过在放电电极的表面上布置含有玻璃的绝缘层，能够抑制放电电极中的导电性无机材料向放电触发部的放电过程的流动。

公开(公告)号：US09408302B2

公开(公告)日：2016-08-02

申请号：US14643230

申请日：2015-03-10

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Byron Williams ,  Shrinivasan Jaganathan ,  David Larkin ,  Dhaval Atul Saraiya

IPC: H05K1/09 ,  H05K1/03 ,  H05K1/16 ,  H01L23/62 ,  H05K1/02 ,  H05K3/46 ,  H05K3/00 ,  H05K1/11

CPC classification number: H01L23/5223 ,  H01L23/49811 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/538 ,  H01L23/62 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/14335 ,  H05K1/0256 ,  H05K1/0257 ,  H05K1/0262 ,  H05K1/0306 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/112 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0088 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/0746 ,  H05K2201/09409 ,  H05K2201/0949 ,  H05K2201/09672 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.