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    Circuit package for electronic systems
    101.
    发明申请
    Circuit package for electronic systems 有权
    电子系统电路封装

    公开(公告)号：US20030206405A1

    公开(公告)日：2003-11-06

    申请号：US10447162

    申请日：2003-05-27

    Applicant: Intel Corporation

    Inventor： Longqiang L. Zu ,  Jennifer A. Hester

    IPC: H05K001/11 ,  H05K001/14

    CPC classification number: H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/0216 ,  H05K1/0224 ,  H05K1/141 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/049 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/10325 ,  H05K2201/10734

    Abstract: A circuit package has been described for routing long traces between an electronic circuit, such as a phase locked loop, and external circuit components. The traces are routed through two substrates. In each substrate, the traces are routed primarily on a layer adjacent to and between a pair ground planes located close to the traces. Degassing apertures are located to the side of the long traces to avoid interfering with the shielding provided by the grounds planes. The circuit package uses two power plated through holes and two ground plated through holes to reduce the noise on the power supply lines. The circuit package also separates the signal carrying plated through holes from the power plated through holes, which reduces noise on the long traces. Noise is further reduced on the long traces by using the ground plated through holes to shield the signal carrying plated through holes from noise generated at the power plated through holes.

    Abstract translation: 已经描述了用于在电子电路（例如锁相环）和外部电路部件之间路由长走线的电路封装。 迹线穿过两个基板。 在每个基板中，迹线主要在邻近于并且位于靠近迹线的一对接地平面之间的层上。 脱气孔位于长轨迹的侧面，以避免与接地平面所提供的屏蔽干扰。 电路封装使用两个电镀通孔和两个接地电镀通孔，以减少电源线上的噪声。 电路封装还将承载电镀通孔的信号与电源通孔分开，从而降低长走线上的噪音。 通过使用接地电镀通孔来屏蔽穿过电镀通孔的信号，从而在电源通孔上产生的噪声，进一步减小了长走线上的噪音。

    Method and adapter for reworking a circuit containing an LGA device
    104.
    发明授权
    Method and adapter for reworking a circuit containing an LGA device 失效
    用于重新加工包含LGA器件的电路的方法和适配器

    公开(公告)号：US06540527B1

    公开(公告)日：2003-04-01

    申请号：US09561401

    申请日：2000-04-28

    Applicant: Vladimir K. Tamarkin

    Inventor： Vladimir K. Tamarkin

    IPC: H01R1200

    CPC classification number: H05K3/225 ,  H01R12/62 ,  H01R12/714 ,  H01R12/721 ,  H01R31/06 ,  H05K1/0292 ,  H05K1/0393 ,  H05K1/117 ,  H05K1/141 ,  H05K3/061 ,  H05K3/108 ,  H05K3/325 ,  H05K3/365 ,  H05K3/42 ,  H05K2201/049 ,  H05K2201/09736 ,  H05K2201/10719 ,  H05K2203/175 ,  Y10S439/957

    Abstract: This invention provides a method for producing an adapter for use with an LGA device. The method includes providing a flexible substrate having a conductive base layer. The method also includes forming a plurality of openings through the flexible substrate. The method further includes defining on the flexible substrate a plurality of vias extending through the openings in the flexible substrate, a plurality of conductive pads electrically connected to the vias, and a plurality of conductive paths extending between adjacent pads, wherein spaces are defined between the pads and the paths to prevent direct contact between the pads and the paths, each of the paths being connected to at least one of a plurality of peripheral pads provided on the flexible substrate. The conductive base layer substantially covers a portion of the substrate surface area. A portion of the base layer may be removed such that remaining portions form conductive branch traces used to connect selected conductive pads with selected conductive paths.

    Abstract translation: 本发明提供一种用于制造用于LGA装置的适配器的方法。 该方法包括提供具有导电基底层的柔性基底。 该方法还包括通过柔性基底形成多个开口。 该方法还包括在柔性基板上限定延伸穿过柔性基板中的开口的多个通孔，电连接到通孔的多个导电焊盘以及在相邻焊盘之间延伸的多个导电路径，其中间隔限定在 垫和路径以防止垫和路径之间的直接接触，每个路径连接到设置在柔性基板上的多个外围垫中的至少一个。 导电基层基本上覆盖基板表面区域的一部分。 可以去除基底层的一部分，使得剩余部分形成用于将所选择的导电焊盘与选定的导电路径连接的导电支路迹线。

    Liquid crystal display device
    105.
    发明申请
    Liquid crystal display device 有权
    液晶显示装置

    公开(公告)号：US20030043314A1

    公开(公告)日：2003-03-06

    申请号：US10074508

    申请日：2002-02-12

    Inventor： Jeoung-Gwen Lee ,  Seung-Je Lee ,  Hyun-Su Park

    IPC: G02F001/1335

    CPC classification number: H05K1/182 ,  G02B6/0031 ,  G02B6/0055 ,  G02B6/0065 ,  G02B6/0083 ,  G02B6/0088 ,  G02B6/009 ,  G02F1/133308 ,  G02F1/1336 ,  G02F1/133608 ,  G02F1/133615 ,  G02F1/13452 ,  G02F2001/133314 ,  G02F2201/465 ,  G06F1/1616 ,  G06F1/1637 ,  G06F1/1654 ,  H04M1/22 ,  H05K1/141 ,  H05K1/148 ,  H05K3/366 ,  H05K2201/049 ,  H05K2201/1003 ,  H05K2201/10189

    Abstract: Disclosed is a liquid crystal display device of which overall size and weight can be minimized. The liquid crystal display device has a light generating unit for generating a light. A light guiding plate guides the light to a display unit for displaying an image. A reflection plate is disposed under the light guiding plate for reflecting the light to the light guiding plate. A receiving container receives the reflection plate, the light guiding plate and the light generating unit. At least one boss is formed on a bottom of the receiving container for preventing the light generating unit from being moved by guiding a position of the light generating unit. Accordingly, the number of the parts installed in the liquid crystal display device can be reduced, and the manufacturing cost can be decreased because the manufacturing process is simplified in comparison with the liquid crystal display device including a separate lamp cover.

    Abstract translation: 公开了一种液晶显示装置，其总体尺寸和重量可以最小化。 液晶显示装置具有用于产生光的光产生单元。 导光板将光引导到用于显示图像的显示单元。 反射板设置在导光板的下方，用于将光反射到导光板。 接收容器容纳反射板，导光板和光产生单元。 在接收容器的底部形成有至少一个凸台，用于通过引导光产生单元的位置来防止光产生单元的移动。 因此，与包括单独的灯罩的液晶显示装置相比，可以减少安装在液晶显示装置中的部件的数量，并且制造成本可以降低，因为制造工艺简化。

    Integrated circuit device/circuit board connection apparatus
    106.
    发明申请
    Integrated circuit device/circuit board connection apparatus 失效

    公开(公告)号：US20030016490A1

    公开(公告)日：2003-01-23

    申请号：US10244876

    申请日：2002-09-17

    Inventor： Joseph P. Miller ,  Sompong P. Olarig ,  Donald J. Stoddard

    IPC: G06F001/16

    CPC classification number: H05K1/023 ,  H05K1/0246 ,  H05K1/141 ,  H05K1/185 ,  H05K2201/049 ,  H05K2201/10022 ,  H05K2201/10734

    Abstract: In a computer system two integrated circuit devices are operatively mounted on the main system board using a pair of interstitial circuit boards sandwiched between the integrated circuit devices and the system board and having substantially smaller footprints than the system board. Each interstitial board has a series of terminating components, representatively resistors, interposed in its circuitry which interconnects the associated integrated circuit board with system board circuitry that, in turn, operatively couples the two integrated circuit boards. The incorporation of the terminating components in the interstitial boards instead of in the system board reduces the circuit complexity of the system board and the required number of layers therein, thereby reducing the cost of the system board and substantially simplifying its signal trace routing design.

    Electronic module having a three dimensional array of carrier-mounted integrated circuit packages
    107.
    发明授权
    Electronic module having a three dimensional array of carrier-mounted integrated circuit packages 有权

    公开(公告)号：US06487078B2

    公开(公告)日：2002-11-26

    申请号：US09524324

    申请日：2000-03-13

    Applicant: Kenneth J. Kledzik ,  Jason C. Engle

    Inventor： Kenneth J. Kledzik ,  Jason C. Engle

    IPC: H05H720

    CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K3/0061 ,  H05K3/3405 ,  H05K3/3421 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/1034 ,  H05K2201/10515 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2201/10924 ,  H01L2924/00

    Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. A second primary embodiment of the invention utilizes a carrier substrate which has a pair of recesses for back-to-back surface mounting of the IC package pair. The two IC packages may be in contact with opposite sides of a heat sink layer embedded within the carrier substrate. Each resulting IC package unit is surface mounted to the main circuit board. A third primary embodiment of the invention incorporates features of both the first and second primary embodiments. One of the packages is mounted on a planar surface of the carrier rightside up, while the other package is mounted on the carrier in a recess upside down. Several variants of this embodiment are possible. Either the IC package that is mounted on the planar surface of the carrier, or the IC package that is mounted within the recess, may be mounted adjacent to the main circuit board. In the former case, the adjacent package of the package unit fits within a recess on the main circuit board. In the latter case, the adjacent package of the package unit mounts on a planar surface of the main circuit board. For any of the three primary main embodiments, the carrier may be equipped with its own set of interconnection leads which interface with the interconnection pads on the main circuit board or connection may be made directly between the leads of one package and the interconnection pads of the circuit board.

    ELECTRONIC MODULE HAVING A THREE DIMENSIONAL ARRAY OF INTEGRATED CIRCUIT PACKAGES
    108.
    发明申请
    ELECTRONIC MODULE HAVING A THREE DIMENSIONAL ARRAY OF INTEGRATED CIRCUIT PACKAGES 有权

    公开(公告)号：US20020135982A1

    公开(公告)日：2002-09-26

    申请号：US09524324

    申请日：2000-03-13

    Inventor： Kenneth J. Kledzik ,  Jason C. Engle

    IPC: H05K007/20

    CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K3/0061 ,  H05K3/3405 ,  H05K3/3421 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/1034 ,  H05K2201/10515 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2201/10924 ,  H01L2924/00

    Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. A second primary embodiment of the invention utilizes a carrier substrate which has a pair of recesses for back-to-back surface mounting of the IC package pair. The two IC packages may be in contact with opposite sides of a heat sink layer embedded within the carrier substrate. Each resulting IC package unit is surface mounted to the main circuit board. A third primary embodiment of the invention incorporates features of both the first and second primary embodiments. One of the packages is mounted on a planar surface of the carrier right-side up, while the other package is mounted on the carrier in a recess upside down. Several variants of this embodiment are possible. Either the IC package that is mounted on the planar surface of the carrier, or the IC package that is mounted within the recess, may be mounted adjacent to the main circuit board. In the former case, the adjacent package of the package unit fits within a recess on the main circuit board. In the latter case, the adjacent package of the package unit mounts on a planar surface of the main circuit board. For any of the three primary main embodiments, the carrier may be equipped with its own set of interconnection leads which interface with the interconnection pads on the main circuit board or connection may be made directly between the leads of one package and the interconnection pads of the circuit board.

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