公开(公告)号：US20090045508A1

公开(公告)日：2009-02-19

申请号：US11837835

申请日：2007-08-13

Applicant: Robert John Romero

Inventor： Robert John Romero

IPC: H01L23/48 ,  H01L21/44 ,  H01L23/52

CPC classification number: H05K1/111 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K2201/09227 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00014

Abstract: Methods, systems, and apparatuses for ball grid array land patterns are provided. A ball grid array land pattern includes a plurality of land pads and electrically conductive traces. The plurality of land pads is arranged in an array of rows and columns. A perimeter edge of the array includes a pair of adjacent oblong shaped land pads. An electrically conductive trace is routed between the pair of adjacent oblong shaped land pads from a land pad positioned in an interior of the array to a location external to the array. The oblong shaped land pads are narrower than standard round land pads, and thus provide more clearance for the routing of traces. The oblong shaped land pads enable more land pads of the land pattern array to be routed external to the array on each routing layer, and thus can save printed circuit board component and assembly costs.

Abstract translation: 提供了球栅排列图案的方法，系统和装置。 球栅阵列平台图案包括多个焊盘和导电迹线。 多个接地焊盘被布置成行和列的阵列。 阵列的周边边缘包括一对相邻的长方形焊盘。 导电迹线在一对相邻的长方形焊盘之间从位于阵列内部的焊盘传送到阵列外部的位置。 长方形的焊盘比标准的圆形焊盘更窄，从而为迹线的布线提供更多的间隙。 长方形的接地焊盘使得焊盘图案阵列的更多焊盘能够在每个布线层上的阵列外部布线，从而可以节省印刷电路板部件和组装成本。

公开(公告)号：US07492325B1

公开(公告)日：2009-02-17

申请号：US11242806

申请日：2005-10-03

Applicant: Peter J. Moosbrugger ,  Tim Meenach

Inventor： Peter J. Moosbrugger ,  Tim Meenach

IPC: H01Q21/00 ,  H01Q3/26

CPC classification number: H01Q21/0093 ,  H01Q21/0087 ,  H05K1/144 ,  H05K2201/09227

Abstract: A modular electronic architecture according to which electrical components are distributed across substantially identical, interconnected circuit elements or assemblies is provided. Scaling of the electronic device can be achieved by selecting different numbers of circuit elements. Embodiments of the present invention may also provide for a compact assembly, formed from interconnection of separate circuit boards in a stack. Particular applications include the provision of beam forming networks in connection with phased array antennas in which the beam forming networks are formed on circuit boards having an area that is about the same size as the area of a circuit board on which the antenna elements are formed.

Abstract translation: 提供了一种模块化电子架构，其中电气部件分布在基本相同的互连电路元件或组件上。 可以通过选择不同数量的电路元件来实现电子设备的缩放。 本发明的实施例还可以提供由堆叠中的单独电路板的互连形成的紧凑组件。 具体应用包括提供与相控阵天线相连的波束形成网络，其中波束形成网络形成在具有与其上形成天线元件的电路板的面积大致相同的大小的电路板上。

公开(公告)号：US20080250373A1

公开(公告)日：2008-10-09

申请号：US11696666

申请日：2007-04-04

Applicant: STEVEN C. BIRD ,  Linda M. Mazaheri ,  Bob Needham ,  Phuong Rosalynn Duong

Inventor： STEVEN C. BIRD ,  Linda M. Mazaheri ,  Bob Needham ,  Phuong Rosalynn Duong

IPC: G06F17/50

CPC classification number: H05K1/113 ,  H05K1/0231 ,  H05K2201/09227 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734

Abstract: Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.

Abstract translation: 提供了用于优化专用集成电路（ASIC）和对应于高密度互连（HDI）印刷电路板（PCB）布局）的其他IC引脚分配的技术。 应用本文描述的技术，可以系统地和策略性地规划引脚分配，例如，为了减少PCB层数量和相关成本，增加信号完整性和速度，减少由ASIC及其支持电路使用的表面积， 与安装在多层PCB上的ASIC的传统设计相比，减少了平面穿孔，并减少了串扰。

公开(公告)号：US20080185181A1

公开(公告)日：2008-08-07

申请号：US11983797

申请日：2007-11-08

Applicant: Charles L. Pfeil

Inventor： Charles L. Pfeil

IPC: H01R12/06 ,  H05K3/40

CPC classification number: H05K1/114 ,  H05K3/429 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10734 ,  Y10T29/49147

Abstract: Various techniques are disclosed for identifying different fanout via configurations that can be created using fanout vias, and then arranging those fanout via configurations in an alternating manner in order to increase the amount and/or area of routing channels available to route traces to the fanout vias. According to some of these techniques, a first fanout via configuration is selected, which can connect a component pin to a first layer of a multilayer printed circuit board. Next, a second fanout via configuration is selected, which can connect a component pin to a second layer of a multilayer printed circuit board different from the first layer. When the printed circuit board is designed, lines of these vias configurations are formed to correspond to a component that will be mounted on the printed circuit board. Each line will have a series of the first fanout via configuration alternating with a series of the second fanout via configuration. Further, two or more fanout via configurations of the same type can be arranged into a via configuration model. A printed circuit board design may then have lines of different via configuration models, such that each line has a series of one type of fanout via configuration model alternating with a series of another type of via fanout configuration model. Alternately or additionally, yet another type of fanout via configuration may be identified. Fanout via configurations of this other type may then be placed along a diagonal line bisecting the area of a printed circuit board design corresponding to the location at which a component will be mounted, in order to preserve routing channel area along the diagonal line.

Abstract translation: 公开了各种技术，用于识别可以使用扇出通孔创建的不同扇出通孔配置，然后以交替方式布置这些扇出通道配置，以便增加可用于将迹线路由到扇出通孔的量和/或面积 。 根据这些技术中的一些，选择第一扇出通孔配置，其可以将部件引脚连接到多层印刷电路板的第一层。 接下来，选择第二扇出通孔配置，其可以将部件引脚连接到与第一层不同的多层印刷电路板的第二层。 当设计印刷电路板时，这些通孔配置的线形成为对应于将安装在印刷电路板上的部件。 每行将通过配置与一系列第二扇出通道配置交替配置一系列第一扇出。 此外，可以将相同类型的两个或多个扇出通孔配置布置成通孔配置模型。 然后，印刷电路板设计可以具有不同通孔配置模型的线，使得每条线通过配置模型具有一系列一种类型的扇出，与一系列另一类型的通孔扇出配置模型交替。 可选地或另外地，可以识别另一种类型的扇出通孔配置。 然后，通过这种其他类型的配置的扇出可以沿着对应于对准于将要安装组件的位置的印刷电路板设计的区域的对角线放置，以便沿着对角线保留路由信道区域。

公开(公告)号：US20080164056A1

公开(公告)日：2008-07-10

申请号：US11650133

申请日：2007-01-05

Applicant: Shawn Robert Gettemy ,  Wei Yao ,  Barry Corlett

Inventor： Shawn Robert Gettemy ,  Wei Yao ,  Barry Corlett

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H05K1/147 ,  G02F1/1345 ,  H05K1/181 ,  H05K2201/09145 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y10T29/4913

Abstract: Compact sub-assemblies of flexible circuits and drivers are provided. The sub-assemblies can occupy less space in an electronic device than conventional sub-assemblies. In one or more embodiments of the present invention, the flexible circuits can be attached to or wires can be disposed on portions of the substrate that previously were unoccupied in conventional sub-assemblies. In one or more embodiments, the sub-assemblies of the present invention also can have wires disposed underneath the driver or vary the width of the wires. In one or more embodiments, the sub-assemblies of the present invention also can have composite wires that occupy less space than wires of conventional sub-assemblies, while still maintaining similar energy flux.

Abstract translation: 提供了柔性电路和驱动器的紧凑型子组件。 子组件在电子设备中的占用空间比传统子组件少。 在本发明的一个或多个实施例中，柔性电路可以附接到或可以将线布置在先前在常规子组件中未被占用的衬底的部分上。 在一个或多个实施例中，本发明的子组件还可以具有布置在驱动器下方的线或者改变线的宽度。 在一个或多个实施例中，本发明的子组件还可以具有与传统子组件的线相比占据更少空间的复合线，同时仍保持相似的能量通量。

公开(公告)号：US20080150122A1

公开(公告)日：2008-06-26

申请号：US11645820

申请日：2006-12-26

Applicant: Cliff Lee ,  David Browning ,  Brian Kelly

Inventor： Cliff Lee ,  David Browning ,  Brian Kelly

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H05K1/114 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/10734 ,  H01L2924/00

Abstract: Methods and apparatus to improve routing density through asymmetric array of vias are described. In one embodiment, a plurality of vias may be asymmetrically distributed relative to the distribution of a plurality of pads. Other embodiments are also described.

Abstract translation: 描述了通过不对称阵列的通孔改善路由密度的方法和装置。 在一个实施例中，多个通孔可以相对于多个焊盘的分布而非对称地分布。 还描述了其它实施例。

公开(公告)号：US07368667B2

公开(公告)日：2008-05-06

申请号：US11200041

申请日：2005-08-10

Applicant: Paul James Brown

Inventor： Paul James Brown

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/114 ,  H05K3/429 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A printed circuit board having micro-vias used to connect a portion of the contacts in a selected row or column to the first internal layer of the board, thereby creating routing channels on the second and subsequent internal layers of the board between selected rows or columns of through-board vias used to connect the remaining contacts and a BGA package adapted to be used with the printed circuit board.

Abstract translation: 一种具有微通孔的印刷电路板，用于将所选行或列中的触点的一部分连接到电路板的第一内层，从而在所选行或列之间的板的第二和随后的内层上创建路由通道 用于连接剩余触点的通孔通孔和适合与印刷电路板一起使用的BGA封装。

公开(公告)号：US07359214B2

公开(公告)日：2008-04-15

申请号：US10952103

申请日：2004-09-28

Applicant: Christopher S. Heard

Inventor： Christopher S. Heard

IPC: H01R12/16

CPC classification number: H05K7/1459 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09227 ,  H05K2201/10189

Abstract: An electronic system having a backplane designed for efficient routing of signal traces. The system includes two or more daughter cards that are connected to multiple other daughter cards in the system. These daughter cards are mounted centrally to the backplane in the system. Connections between those two daughter cards and the backplane are made through electrical connectors that are distributed in columns along the length of the daughter cards. The connectors are positioned with space between the connectors. The space forms routing channels such that signals that must be connected to the central cards from a daughter cards on either side may be routed through the routing channels.

Abstract translation: 具有设计用于有效地路由信号迹线的背板的电子系统。 该系统包括两个或多个子卡，其连接到系统中的多个其他子卡。 这些子卡集中安装在系统的背板上。 这两个子卡和背板之间的连接通过沿着子卡长度分列在列中的电连接器制成。 连接器在连接器之间具有空间。 空间形成路由信道，使得必须从任一侧的子卡连接到中央卡的信号可以通过路由信道路由。

公开(公告)号：US07341887B2

公开(公告)日：2008-03-11

申请号：US10977157

申请日：2004-10-29

Applicant: Chee Wai Wong ,  Chee Hoo Lee

Inventor： Chee Wai Wong ,  Chee Hoo Lee

IPC: H01L21/58 ,  H01L21/60

CPC classification number: H01L23/5286 ,  H01L23/49838 ,  H01L23/562 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09418 ,  H05K2201/10719 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Integrate circuit die terminal arrangements and configurations for mounting an integrate circuit die on a package substrate to reduce package transmission paths. In one embodiment, terminals for signals sensitive to trace length outside a die are arranged at the corners of the die. The die is mounted on a package substrate in an angle with respect to a package substrate to point the corners of the die at the edges of the package substrate to reduce trace length outside the die. The center of the die may or may not coincide with the center of the substrate. In one embodiment, when compare to a centered, non-rotated die mounting position, mounting a die with corners pointing at the edges of the package substrate does not cause significant differences in substrate warpage.

Abstract translation: 集成电路管芯端子布置和配置，用于将集成电路管芯安装在封装衬底上，以减少封装传输路径。 在一个实施例中，对于在管芯外部的迹线长度敏感的信号的端子设置在管芯的角部。 模具相对于封装衬底以一定角度安装在封装衬底上，以将芯片的角部指向封装衬底的边缘，以减小管芯外部的迹线长度。 管芯的中心可以与衬底的中心重合或者不一致。 在一个实施例中，当与居中的未旋转的模具安装位置相比时，安装具有指向封装基板边缘的拐角的模具不会引起基板翘曲的显着差异。

公开(公告)号：US20070194433A1

公开(公告)日：2007-08-23

申请号：US10592948

申请日：2004-03-19

Applicant: Motoo Suwa ,  Yoshinori Miyaki ,  Toru Hayashi ,  Ryoichi Sano ,  Shigezumi Matsui ,  Takanobu Naruse ,  Takashi Sato ,  Hisashi Shiota

Inventor： Motoo Suwa ,  Yoshinori Miyaki ,  Toru Hayashi ,  Ryoichi Sano ,  Shigezumi Matsui ,  Takanobu Naruse ,  Takashi Sato ,  Hisashi Shiota

IPC: H01L23/12

CPC classification number: H01L23/552 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0216 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic circuit includes a first semiconductor device (4) and a second semiconductor device (3) on a mounting substrate. The mounting substrate includes a plurality of mounting substrate lines (201 to 204) which are connected in common with external terminals of a plurality of bits of the first semiconductor device and external terminals of a plurality of bits of the second semiconductor device for every bit. The mounting substrate lines have lengths thereof from the external terminals of the first semiconductor device to the external terminals of the second semiconductor device made unequal for respective bits. Assembling lines (361 to 364) which reach connecting electrodes of a semiconductor chip from the external terminals of the second semiconductor device have made lengths thereof unequal for respective bits. Here, the unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines. According to such a constitution, it is unnecessary to set lengths between the external terminals of the second semiconductor device and the connecting electrodes of the semiconductor chip equal.

Abstract translation: 电子电路包括在安装基板上的第一半导体器件（4）和第二半导体器件（3）。 安装基板包括与第一半导体器件的多个位的外部端子和第二半导体器件的多个位的外部端子共同连接的多个安装基板线（201〜204）。 安装基板线具有从第一半导体器件的外部端子到对于各个位不相等的第二半导体器件的外部端子的长度。 从第二半导体器件的外部端子到达半导体芯片的连接电极的组装线（361至364）使其长度对于各个位不相等。 这里，安装基板线的不等长度具有抵消装配线的不等长度的关系。 根据这种结构，不需要在第二半导体器件的外部端子和半导体芯片的连接电极之间设置长度相等。