公开(公告)号：US20060220233A1

公开(公告)日：2006-10-05

申请号：US11389330

申请日：2006-03-27

Applicant: Hideki Ito ,  Masanori Hongo ,  Masami Fukuyama ,  Hiroyuki Taguchi ,  Hideki Takagi

Inventor： Hideki Ito ,  Masanori Hongo ,  Masami Fukuyama ,  Hiroyuki Taguchi ,  Hideki Takagi

IPC: H01L23/34

CPC classification number: H05K3/3442 ,  H01L21/4857 ,  H01L23/15 ,  H01L23/49805 ,  H01L24/97 ,  H01L33/486 ,  H01L33/62 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H05K2201/09472 ,  H05K2201/09845 ,  H05K2201/10106 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: A package of the present invention has a laminate structure of a plurality of ceramic layers, and includes a cavity for housing a light emitting element. A mount surface is defined on a side surface parallel with the depth direction of the cavity. A pair of external electrodes each including a charged electrode portion and a coated electrode portion are formed over the entire length in the laminating direction at two corners defined by intersection of the mount surface and two side surfaces perpendicular to the mount surface. When the package is mounted, a pair of charged electrode portions and a pair of coated electrode portions are soldered to a surface of a substrate.

Abstract translation: 本发明的封装具有多个陶瓷层的叠层结构，并且包括用于容纳发光元件的空腔。 安装表面限定在与空腔的深度方向平行的侧表面上。 在安装面和与安装面垂直的两个侧面的交点形成的两个角处，在层叠方向的整个长度上形成有一对包含带电电极部分和涂覆电极部分的外部电极。 当安装封装时，将一对充电电极部分和一对涂覆的电极部分焊接到基板的表面。

公开(公告)号：US20060185892A1

公开(公告)日：2006-08-24

申请号：US11335125

申请日：2006-01-19

Applicant: Volker Guengerich ,  Horst Theuss

Inventor： Volker Guengerich ,  Horst Theuss

IPC: H05K1/16

CPC classification number: H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/66 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2223/6611 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45033 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45572 ,  H01L2224/45573 ,  H01L2224/45686 ,  H01L2224/45688 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/4899 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2224/86205 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/1903 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0243 ,  H05K3/341 ,  H05K2201/09472 ,  H05K2201/09809 ,  H05K2201/10287 ,  H05K2201/10356 ,  H01L2924/00014 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/83205

Abstract: A semiconductor device with micro connecting elements and method for producing the same disclosed. In one embodiment, the semiconductor device includes a number of micro connecting elements for the high-frequency coupling of components of the semiconductor device. The micro connecting elements have an at least three-layered structural form with a first layer of conducting material, a second layer of insulating material and a third layer of conducting material. In this configuration, the first and third layers and extend along a common center line and shield one another against electromagnetic interference fields. The first and third layers and are fixed on correspondingly adapted pairs of contact terminal areas of the components.

Abstract translation: 具有微连接元件的半导体器件及其制造方法。 在一个实施例中，半导体器件包括用于半导体器件的部件的高频耦合的多个微连接元件。 微连接元件具有至少三层结构形式，其具有第一层导电材料，第二层绝缘材料和第三层导电材料。 在该配置中，第一和第三层沿公共中心线延伸并相互屏蔽电磁干扰场。 第一和第三层并且固定在部件的相应适应的接触端子区域对上。

公开(公告)号：US07051433B1

公开(公告)日：2006-05-30

申请号：US10431388

申请日：2003-05-08

Applicant: Herman Kwong ,  Larry E. Marcanti ,  Aneta Wyrzykowska

Inventor： Herman Kwong ,  Larry E. Marcanti ,  Aneta Wyrzykowska

IPC: H01K3/10

CPC classification number: H01L23/552 ,  H01L23/642 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/48472 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/183 ,  H05K3/3421 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/10371 ,  H05K2201/10515 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A technique for eliminating electrically conductive vias is disclosed. In one embodiment, the technique is realized as an improved multilayer circuit board for eliminating electrically conductive vias. The multilayer circuit board has a top layer and a buried layer separated by at least one dielectric layer, wherein the buried layer includes an electrically conductive power plane portion and an electrically conductive ground plane portion. The improvement comprises a cavity in the multilayer circuit board extending through the top layer and the at least one dielectric layer so as to expose at least a portion of the power plane portion and the ground plane portion of the buried layer within the cavity. The cavity is sized to accommodate an electronic component therein such that the electronic component makes electrical contact with the exposed portion of the power plane portion and the ground plane portion of the buried layer, thereby eliminating the need for electrically conductive vias electrically connected to the power plane portion and the ground plane portion of the buried layer.

公开(公告)号：US07042149B2

公开(公告)日：2006-05-09

申请号：US10456584

申请日：2003-06-09

Applicant: Hirotaka Shigeno

Inventor： Hirotaka Shigeno

IPC: H01J1/62

CPC classification number: G02F1/13458 ,  G02F1/13452 ,  H05K3/361 ,  H05K2201/09472 ,  H05K2201/09909

Abstract: A circuit array substrate 10 includes pixel and connecting edge sections 80 and 90. Connecting edge section 90 is provided with edge portions 5a and shoulder portions 55 of transparent thin resin film 5 over which terminal pins 101 of tape carrier packages (TCP) 100 are disposed. Terminal pins 101 are connected to connecting pads 14 at their contact portions 103. Shoulder portions 55 prevent a coated photoresist film from being excessive in depth and residues of the photoresist film from being left in the foot of edge face 5a in the step of forming metal reflective pixel electrodes. Thus, no residue of the metal film exists after its etching treatment in that step so that no electrical short circuits are caused between connecting pads 14 and adjacent terminal pins 101.

Abstract translation: 电路阵列基板10包括像素和连接边缘部分80和90。 连接边缘部分90设置有透明薄树脂膜5的边缘部分5a和肩部55，在该部分上设有带状载体封装（TCP）100的端子引脚101。 端子销101在其接触部分103处连接到连接焊盘14。 在形成金属反射像素电极的步骤中，肩部55防止涂覆的光致抗蚀剂膜的深度过大，光刻胶膜的残留物残留在边缘面5a的脚中。 因此，在该步骤中的蚀刻处理之后，不存在金属膜残留物，使得在连接焊盘14和相邻的端子引脚101之间不产生电气短路。

公开(公告)号：US07019407B2

公开(公告)日：2006-03-28

申请号：US10707609

申请日：2003-12-24

Applicant: Yu-Wen Chen ,  Ming-Lun Ho ,  Shih-Chang Lee ,  Chih-Huang Chang

Inventor： Yu-Wen Chen ,  Ming-Lun Ho ,  Shih-Chang Lee ,  Chih-Huang Chang

IPC: H01L23/48

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/81136 ,  H01L2224/81194 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/112 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/09518 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2224/05599

Abstract: A flip chip package structure comprising a chip, a substrate, at least a first bump and a plurality of second bumps is provided. The chip has a first bump-positioning region and the substrate has a second bump-positioning region. The substrate has at least a first hole and multiple second holes. The first hole and the second holes are located within the second bump-positioning region. The first hole has a depth greater than that of the second hole. The first bump is set up between the first bump-positioning region of the chip and the second bump-positioning region of the substrate. The first bump is bonded to the substrate through the first holes. The second bumps are set up between the first bump-positioning region of the chip and the second bump-positioning region of the substrate. The second bumps are bonded to the substrate through the second holes. The first bump has a volume greater than the volume of the second bump.

Abstract translation: 提供了包括芯片，基板，至少第一凸块和多个第二凸块的倒装芯片封装结构。 芯片具有第一凸块定位区域，并且基板具有第二凸起定位区域。 衬底具有至少第一孔和多个第二孔。 第一孔和第二孔位于第二凸起定位区域内。 第一孔的深度大于第二孔的深度。 第一凸块设置在芯片的第一凸点定位区域和衬底的第二凸起定位区域之间。 第一凸起通过第一孔结合到基底。 在芯片的第一凸块定位区域和基板的第二凸块定位区域之间设置第二凸块。 第二凸起通过第二孔结合到基底。 第一凸起的体积大于第二凸块的体积。

公开(公告)号：US20050286240A1

公开(公告)日：2005-12-29

申请号：US11150741

申请日：2005-06-10

Applicant: Yasuhiro Sakamoto ,  Tomoyuki Sagara ,  Yoshinori Nakajima

Inventor： Yasuhiro Sakamoto ,  Tomoyuki Sagara ,  Yoshinori Nakajima

IPC: H01R12/51 ,  H05K1/14 ,  H05K3/32 ,  H05K3/36

CPC classification number: B41J2/14209 ,  B41J2/1609 ,  B41J2/1623 ,  B41J2/1631 ,  B41J2/1632 ,  B41J2/1635 ,  B41J2/1642 ,  B41J2/1643 ,  B41J2002/14491 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/0352 ,  H05K2201/09472

Abstract: An electrode connection structure between outer lead(s) of TCP(s), being first circuit board(s), and actuator member electrode(s) for connection to external circuitry, being second circuit board(s); actuator member(s) electrode(s) for connection to external circuitry being formed in or on floor(s) of recess(es) which is/are step(s) smaller in magnitude than thickness(es) of outer lead(s) protruding from polyimide substrate(s) of TCP(s); adhesive(s) having thickness(es) more or less equal to difference(s) between step(s) and thickness(es) of outer lead(s); and outer lead(s) being electrically and mechanically connected to electrode(s) for connection to external circuitry.

Abstract translation: 作为第一电路板的TCP外部引线之间的电极连接结构和用于连接到外部电路的致动器构件电极是第二电路板; 用于连接到外部电路的致动器构件电极形成在凹槽的一个或多个地板中，所述凹部的尺寸比外引线的厚度小， 从TCP的一个或多个聚酰亚胺基底突出; 厚度（es）或多或少等于外引线的台阶和厚度之间的差异的粘合剂; 并且外部引线电连接和机械连接到用于连接到外部电路的电极。

公开(公告)号：US06980014B2

公开(公告)日：2005-12-27

申请号：US10379221

申请日：2003-03-04

Applicant: Salman Akram ,  Alan G. Wood ,  Warren M. Farnworth

Inventor： Salman Akram ,  Alan G. Wood ,  Warren M. Farnworth

IPC: G01R1/04 ,  H05K1/11 ,  H05K1/14 ,  H05K3/34 ,  G01R31/02

CPC classification number: H05K7/1061 ,  B33Y10/00 ,  B33Y30/00 ,  B33Y80/00 ,  G01R1/0408 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/07378 ,  G01R3/00 ,  H01L23/32 ,  H01L23/49827 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2224/8114 ,  H01L2224/81385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K1/112 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/049 ,  H05K2201/09472 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2203/167 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: An interposer including a fence that receives and aligns a semiconductor device, such as a flip-chip type semiconductor device, with a substrate. The fence may include edges that are configured to progressively align a semiconductor device with the substrate. The fence may also include one or more laterally recessed regions to facilitate rough alignment of a semiconductor device with the substrate. Methods for fabricating the fence include the use of stereolithographic and molding processes. When stereolithography is used to fabricate the fence, a machine vision system that includes at least one camera operably associated with a computer may be used to control a stereolithography apparatus and facilitates recognition of the position and orientation of substrates on and around which material is to be applied in one or more layers to form the fence. As a result, the substrates need not be precisely mechanically aligned.

Abstract translation: 一种插入器，包括接收半导体器件（例如倒装芯片型半导体器件）和衬底的栅栏。 栅栏可以包括被配置为逐渐地将半导体器件与衬底对准的边缘。 栅栏还可以包括一个或多个侧向凹入的区域，以便于半导体器件与衬底的粗略对准。 围栏的制造方法包括使用立体光刻和成型工艺。 当使用立体光刻制造栅栏时，可以使用包括与计算机可操作地相关联的至少一个照相机的机器视觉系统来控制立体光刻设备，并且有助于识别材料在其上和周围的位置和取向 施加在一个或多个层中以形成栅栏。 因此，基板不需要精确地机械对准。

公开(公告)号：US06972381B2

公开(公告)日：2005-12-06

申请号：US10190515

申请日：2002-07-09

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/552 ,  H05K1/11 ,  H05K1/18 ,  H05K3/28 ,  H05K3/32 ,  H05K1/16

CPC classification number: H01L24/29 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/4985 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/83095 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83859 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/90 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/112 ,  H05K1/189 ,  H05K3/28 ,  H05K3/284 ,  H05K3/323 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10674 ,  H05K2203/0278 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05644

Abstract: A semiconductor device and a method of manufacturing the semiconductor device includes: a first step of interposing a thermosetting anisotropic conductive material 16 between a substrate 12 and a semiconductor chip 20; a second step in which pressure and heat are applied between the semiconductor chip 20 and the substrate 12, an interconnect pattern 10 and electrodes 22 are electrically connected, and the anisotropic conductive material 16 is spreading out beyond the semiconductor chip 20 and is cured in the region of contact with the semiconductor chip 20; and a third step in which the region of the anisotropic conductive material 16 other than the region of contact with the semiconductor chip 20 is heated.

Abstract translation: 半导体器件和半导体器件的制造方法包括：在基板12和半导体芯片20之间插入热固性各向异性导电材料16的第一步骤; 在半导体芯片20和基板12之间施加压力和热量的第二步骤，布线图案10和电极22电连接，并且各向异性导电材料16扩散到半导体芯片20之外并在 与半导体芯片20的接触区域; 以及第三步骤，其中除了与半导体芯片20的接触区域之外的各向异性导电材料16的区域被加热。

公开(公告)号：US20050239237A1

公开(公告)日：2005-10-27

申请号：US11112739

申请日：2005-04-22

Applicant: Frank Puschner ,  Wolfgang Schindler ,  Gunter Tutsch

Inventor： Frank Puschner ,  Wolfgang Schindler ,  Gunter Tutsch

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L23/498 ,  H01L23/50 ,  H05K3/34

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2201/0394 ,  H05K2201/09472 ,  Y02P70/613 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: BGA chip module and method for producing the BGA chip module by providing a carrier, forming holes at points at which bonding points of the BGA chip module are to be produced, forming metallization areas on an upper side of the carrier and covering the holes, connecting bonding points of a chip to the metallization areas, and introducing bonding elements into the holes.

Abstract translation: BGA芯片模块和通过提供载体制造BGA芯片模块的方法，在要制造BGA芯片模块的接合点的点处形成孔，在载体的上侧形成金属化区域并覆盖孔 将芯片的接合点连接到金属化区域，并将结合元件引入孔中。

公开(公告)号：US06936502B2

公开(公告)日：2005-08-30

申请号：US10437006

申请日：2003-05-14

Applicant: Aneta Wyrzykowska ,  Herman Kwong ,  Luigi Difilippo

Inventor： Aneta Wyrzykowska ,  Herman Kwong ,  Luigi Difilippo

IPC: H05K1/11 ,  H05K3/30 ,  H05K3/46 ,  H01L21/60 ,  H05K3/32

CPC classification number: H05K1/112 ,  H01L2224/14 ,  H01L2224/17 ,  H01L2924/00014 ,  H05K3/303 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/10318 ,  H05K2201/10424 ,  H05K2201/10659 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A method for implementing a circuit component on a surface of a multilayer circuit board is provided. The circuit component includes a plurality of pins and the circuit board includes a plurality of electrically conductive vias penetrating at least one layer of the circuit board and being arranged so as to form at least one channel for routing one or more traces at one or more signal layers of the circuit board. The method comprises the step of forming at least one pin of the plurality of pins of the circuit component to have a length compatible with a depth of a corresponding via of the circuit board.

Abstract translation: 提供一种在多层电路板的表面上实现电路元件的方法。 电路部件包括多个引脚，并且电路板包括穿透电路板的至少一个层的多个导电通孔，并被布置成形成用于在一个或多个信号处路由一个或多个迹线的至少一个通道 层的电路板。 该方法包括以下步骤：形成电路部件的多个引脚中的至少一个引脚以具有与电路板的相应通孔的深度相兼容的长度。