公开(公告)号：US20160073501A1

公开(公告)日：2016-03-10

申请号：US14482498

申请日：2014-09-10

Applicant: International Business Machines Corporation

Inventor： Aaron M. Hegrenes ,  Nathan D. Karl ,  Robert J. Monahan ,  Stephen P. Mroz ,  Christopher L. Tuma

IPC: H05K1/14 ,  H05K3/36

CPC classification number: H05K1/144 ,  G06F1/18 ,  G06F1/183 ,  H05K3/36 ,  H05K7/142 ,  H05K7/1487 ,  H05K13/00 ,  H05K2201/042 ,  H05K2201/10378 ,  H05K2201/2018 ,  Y10T29/49828

Abstract: A method and apparatus are provided for implementing simultaneously connecting of multiple devices in a multi-tiered, multi-directional, enhanced tolerance system with mechanical support structures. A main system planar assembly and an elevated planar assembly share a direct connection provided by a plurality of connectors with no cables. A mechanical support bracket is attached to a top surface of the main system planar assembly positioning and supporting the elevated planar assembly spaced appropriately for accurately connecting respective connectors with respective chassis connectors. The elevated planar assembly includes a stiffening component to facilitate proper spacing between upper and lower levels of respective connectors and tool-less insertion and extraction of the elevated planar assembly.

公开(公告)号：US09282646B2

公开(公告)日：2016-03-08

申请号：US14164245

申请日：2014-01-26

Applicant: Unimicron Technology Corp.

Inventor： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

IPC: H05K1/11 ,  H05K3/10 ,  C25D1/00 ,  H05K3/46 ,  H05K3/42

CPC classification number: H01L21/4857 ,  C25D1/003 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D7/12 ,  H05K1/113 ,  H05K3/10 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0733 ,  Y10T29/49155

Abstract: A manufacturing method of an interposed substrate is provided. A metal-stacked layer comprising a first metal layer, an etching stop layer and a second metal layer is formed. A patterned conductor layer is formed on the first metal layer, wherein the patterned conductor layer exposes a portion of the first metal layer. A plurality of conductive pillars is formed on the patterned conductor layer, wherein the conductive pillars are separated from each other and stacked on a portion of the patterned conductor layer. An insulating material layer is formed on the metal-stacked layer, wherein the insulating material layer covers the portion of the first metal layer and encapsulates the conductive pillars and the other portion of the patterned conductor layer. The metal-stacked layer is removed to expose a lower surface opposite to an upper surface of the insulating material layer and a bottom surface of the patterned conductor layer.

Abstract translation: 提供了一种插入式基板的制造方法。 形成包括第一金属层，蚀刻停止层和第二金属层的金属层叠层。 图案化的导体层形成在第一金属层上，其中图案化的导体层露出第一金属层的一部分。 在图案化的导体层上形成多个导电柱，其中导电柱彼此分离并堆叠在图案化的导体层的一部分上。 在金属堆叠层上形成绝缘材料层，其中绝缘材料层覆盖第一金属层的部分并且封装导电柱和图案化导体层的另一部分。 去除金属层叠层以露出与绝缘材料层的上表面相反的下表面和图案化导体层的底表面。

公开(公告)号：US20160044789A1

公开(公告)日：2016-02-11

申请号：US14819579

申请日：2015-08-06

Applicant: IBIDEN CO., LTD.

Inventor： Keisuke SHIMIZU ,  Makoto TERUI ,  Ryojiro TOMINAGA ,  Yuichi NAKAMURA

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/22 ,  H05K3/28 ,  H05K3/40 ,  H05K3/06 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/185 ,  H05K1/0224 ,  H05K3/305 ,  H05K3/429 ,  H05K3/4694 ,  H05K2201/09536 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/2072

Abstract: A wiring board with a cavity for a built-in electronic component includes a conductor layer including a conductor circuit layer and a plane layer, and an insulating layer laminated on the conductor layer and having a cavity such that the cavity is forming an exposed portion of the plane layer and formed to mount a built-in electronic component on the exposed portion of the plane layer. The plane layer has a recess structure formed in an outer peripheral portion in the exposed portion of the plane layer.

Abstract translation: 具有用于内置电子部件的空腔的布线板包括导体层，该导体层包括导体电路层和平面层，以及绝缘层，层压在导体层上并具有空腔，使得空腔形成暴露部分 该平面层并形成为将内置的电子部件安装在平面层的暴露部分上。 平面层具有形成在平面层的露出部分的外周部分中的凹陷结构。

公开(公告)号：US20160043489A1

公开(公告)日：2016-02-11

申请号：US14452197

申请日：2014-08-05

Applicant: INFINERA CORP.

Inventor： John Michael Coronati ,  Eugene Messenger ,  Michael Sipics ,  Joseph Edward Riska ,  Jiaming Zhang

IPC: H01R12/71 ,  H01R43/26 ,  H01R4/38

CPC classification number: H01R12/714 ,  H01L31/02002 ,  H01R12/7011 ,  H01R12/73 ,  H05K3/225 ,  H05K3/325 ,  H05K3/368 ,  H05K3/4015 ,  H05K2201/0373 ,  H05K2201/068 ,  H05K2201/09427 ,  H05K2201/10121 ,  H05K2201/10234 ,  H05K2201/10378 ,  H05K2201/10393 ,  H05K2203/176

Abstract: An apparatus including a bridge member and a clamp is disclosed. The bridge member is positioned in a first plane and has a substrate with a first surface and a second surface; and a plurality of distinct conductive pillars formed on the second surface of the substrate. The clamp has a body, a proximal end and a distal end. The body is positioned in a second plane above the first plane with the second plane being within 2 degrees of parallel to the first plane. The proximal end is positioned along the second plane; and the distal end has a plurality of prongs. The distal end is offset from the second plane in a direction toward the bridge member such that each prong contacts the first surface of the substrate.

Abstract translation: 公开了一种包括桥构件和夹具的装置。 桥构件定位在第一平面中并且具有带有第一表面和第二表面的基底; 以及形成在所述基板的第二表面上的多个不同的导电柱。 夹具具有主体，近端和远端。 身体位于第一平面上方的第二平面中，第二平面在与第一平面平行的2度内。 近端沿着第二平面定位; 并且远端具有多个插脚。 远端在朝向桥接件的方向上偏离第二平面，使得每个尖头接触基板的第一表面。

公开(公告)号：US09253894B2

公开(公告)日：2016-02-02

申请号：US13973766

申请日：2013-08-22

Applicant: Wintec Industries, Inc.

Inventor： Kong-Chen Chen

IPC: H01L23/00 ,  H05K3/30 ,  H01L21/66 ,  H01L21/67 ,  H01L23/04 ,  H01L23/10 ,  H01L23/40 ,  H01L23/544 ,  H01L25/065 ,  H05K1/14 ,  H05K3/32 ,  H05K1/16 ,  H05K7/20 ,  H01L23/48 ,  H05K1/02 ,  H05K3/22

CPC classification number: H05K3/303 ,  H01L21/67259 ,  H01L22/32 ,  H01L22/34 ,  H01L23/041 ,  H01L23/10 ,  H01L23/4093 ,  H01L23/481 ,  H01L23/544 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/72 ,  H01L25/0655 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2223/54466 ,  H01L2223/54473 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29444 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/0268 ,  H05K1/0296 ,  H05K1/144 ,  H05K1/16 ,  H05K3/222 ,  H05K3/325 ,  H05K7/20436 ,  H05K2201/0314 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2203/167 ,  Y10T29/49004 ,  Y10T29/49133 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: An electronic assembly including a substrate, an electronic component, a fixture, and a housing. The substrate includes a first contact array. The electronic component includes a second contact array. The fixture includes an opening adapted to position the electronic component on the substrate and to connect the second contact array to the first contact array when the fixture is aligned at a first position on the substrate. The housing is adapted to hold the substrate populated with the electronic component. The housing includes a first conductive pathway adapted to connect from an external surface at the housing to the substrate in a serial continuous conductive path when the fixture is aligned at the first position on the substrate. The electronic assembly includes a sensing device connected to the continuous conductive path to detect the integrity of the electronic assembly.

Abstract translation: 一种包括基板，电子部件，固定装置和壳体的电子组件。 衬底包括第一接触阵列。 电子部件包括第二接触阵列。 所述固定装置包括适于将所述电子部件定位在所述基板上并且当所述固定装置对准在所述基板上的第一位置时将所述第二接触阵列连接到所述第一接触阵列的开口。 壳体适于保持充满电子部件的基板。 壳体包括第一导电路径，当第一导电路径适于在该基座上的第一位置处对齐时，以串联连续的导电路径从壳体的外表面连接到衬底。 电子组件包括连接到连续导电路径的感测装置，以检测电子组件的完整性。

公开(公告)号：US20160021756A1

公开(公告)日：2016-01-21

申请号：US14730250

申请日：2015-06-04

Applicant: APPLE INC.

Inventor： Meng Chi Lee ,  Shankar Pennathur ,  Scott L. Gooch ,  Dennis R. Pyper ,  Amir Salehi

IPC: H05K1/18 ,  H05K1/14 ,  H05K3/36 ,  H05K3/32 ,  H05K3/30 ,  H05K1/11 ,  H05K3/28

CPC classification number: H05K1/189 ,  H01L23/4012 ,  H01L25/0652 ,  H01L25/0655 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K3/284 ,  H05K3/361 ,  H05K3/4015 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2203/1316 ,  Y10T29/49128

Abstract: Readily modifiable and customizable, low-area overhead interconnect structures for forming connections between a system-in-a-package module and other components in an electronic device. One example may provide an interposer for providing an interconnection between a system-in-a-package module and other components in an electronic device. Another may provide a plurality of conductive pins or contacts to form interconnect paths between a module and other components.

Abstract translation: 易于修改和可定制的低面积架空互连结构，用于在系统级封装模块和电子设备中的其他组件之间形成连接。 一个示例可以提供用于在电子设备中的系统级封装模块和其它部件之间提供互连的插入器。 另一个可以提供多个导电引脚或触点以在模块和其它部件之间形成互连路径。

公开(公告)号：US20160020164A1

公开(公告)日：2016-01-21

申请号：US14799846

申请日：2015-07-15

Applicant: IBIDEN CO., LTD.

Inventor： Makoto TERUI ,  Ryojiro Tominaga ,  Masatoshi Kunieda ,  Noriki Sawada

IPC: H01L23/498 ,  C23C18/18 ,  C23C18/16 ,  C23C18/42 ,  C23C18/31 ,  H01L21/48 ,  C23C18/32

CPC classification number: H01L23/49822 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/31 ,  C23C18/32 ,  C23C18/42 ,  C25D7/00 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15313 ,  H05K1/186 ,  H05K3/4007 ,  H05K3/4644 ,  H05K3/4694 ,  H05K3/4697 ,  H05K2201/10378

Abstract: A wiring substrate includes a first outermost conductor layer, a first outermost insulating layer covering the first conductor layer, a second outermost conductor layer formed on opposite side of the first conductor layer, and a second outermost insulating layer covering the second conductor layer. The first insulating layer has first openings such that the first openings are exposing first conductor pads including portions of the first conductor layer, the second insulating layer has second openings such that the second openings are exposing second conductor pads including portions of the second conductor layer, each of the first conductor pads has a first plating layer recessed with respect to outer surface of the first insulating layer, and each of the second conductor pads has a second plating layer formed flush with outer surface of the second insulating layer or having bump shape protruding from the outer surface of the second insulating layer.

Abstract translation: 布线基板包括第一最外导体层，覆盖第一导体层的第一最外绝缘层，形成在第一导体层相对侧的第二最外导体层和覆盖第二导体层的第二最外绝缘层。 第一绝缘层具有第一开口，使得第一开口暴露包括第一导体层的部分的第一导体焊盘，第二绝缘层具有第二开口，使得第二开口暴露包括第二导体层的部分的第二导体焊盘， 每个第一导体焊盘具有相对于第一绝缘层的外表面凹陷的第一镀层，并且每个第二导体焊盘具有与第二绝缘层的外表面齐平或具有突出形状的凸起形状的第二镀层 从第二绝缘层的外表面。

公开(公告)号：US09241408B2

公开(公告)日：2016-01-19

申请号：US13927251

申请日：2013-06-26

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuo Hattori ,  Tadateru Yamada ,  Isamu Fujimoto

IPC: H05K1/18 ,  H01G2/02 ,  H01G2/06 ,  H05K3/34

CPC classification number: H05K1/18 ,  H01G2/02 ,  H01G2/06 ,  H05K1/181 ,  H05K3/3442 ,  H05K2201/09145 ,  H05K2201/10015 ,  H05K2201/10378 ,  H05K2201/2045 ,  Y02P70/611

Abstract: In an electronic component, upper surface electrodes are located on one main surface of an insulating substrate of an interposer on which a multilayer ceramic capacitor is mounted. The insulating substrate has substantially the same shape as that of the multilayer ceramic capacitor, viewed from a direction perpendicular or substantially perpendicular to the main surface, and has the multilayer ceramic capacitor mounted thereon so that the length direction of the multilayer ceramic capacitor substantially coincides with the length direction of the insulating substrate. The insulating substrate includes cutouts that include connection electrodes, respectively, and that are located at the four corners viewed from the direction perpendicular or substantially perpendicular to the main surface. The upper surface electrodes on the one main surface are connected via the connection electrodes to lower surface electrodes, respectively, that are located on the other main surface and are connected to a circuit board.

Abstract translation: 在电子部件中，上表面电极位于其上安装有多层陶瓷电容器的插入器的绝缘基板的一个主表面上。 绝缘基板的形状与多层陶瓷电容器的形状基本相同，从与主表面垂直或大致垂直的方向观察，并将多层陶瓷电容器安装在其上，使多层陶瓷电容器的长度方向基本上与 绝缘基板的长度方向。 绝缘基板包括分别包括连接电极并且位于从垂直于或基本上垂直于主表面的方向观察的四个拐角处的切口。 一个主表面上的上表面电极经由连接电极分别连接到位于另一个主表面上并连接到电路板的下表面电极。

公开(公告)号：US09226396B2

公开(公告)日：2015-12-29

申请号：US13797355

申请日：2013-03-12

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H05K1/09 ,  H05K1/00 ,  H05K1/16 ,  H05K1/11 ,  H05K7/10 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K1/0306 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3731 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/09 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/0323

Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

Abstract translation: 中间体及其制备方法在本文中公开。 在一个实施例中，插入件包括具有第一和第二相对面的表面和多个孔的区域，每个孔从第一表面朝向第二表面沿第一方向延伸，其中氧化铝沿每个孔的壁延伸; 多个导电连接元件，其沿第一方向延伸，主要由铝构成，并通过至少氧化铝彼此电隔离; 第一导电路径，设置在第一表面处，用于与插入件外部的第一部件连接; 以及设置在所述第二表面处用于与所述插入件外部的第二部件连接的第二导电路径，其中所述第一和第二导电路径通过至少一些所述连接元件电连接。

公开(公告)号：US20150359098A1

公开(公告)日：2015-12-10

申请号：US14758195

申请日：2013-07-24

Applicant: HANA MICRON INC.

Inventor： Jin Young Ock

IPC: H05K1/14 ,  H05K1/18 ,  H05K3/40 ,  H05K3/18 ,  H05K3/30 ,  H05K3/32 ,  H05K1/11 ,  H05K3/26

CPC classification number: H05K1/14 ,  H01L21/486 ,  H01L21/568 ,  H01L23/147 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2518 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/19105 ,  H05K1/115 ,  H05K1/181 ,  H05K1/185 ,  H05K3/181 ,  H05K3/26 ,  H05K3/303 ,  H05K3/32 ,  H05K3/4038 ,  H05K3/4602 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/0191 ,  H05K2203/1469 ,  Y02P70/611 ,  Y10T29/49131 ,  Y10T29/49149 ,  H01L2924/00

Abstract: The present invention relates to a circuit board having an interposer embedded therein, including: an interposer, the top side and back side of which are electrically connected by a first through-electrode; and a molding member having the interposer embedded therein and the top side and back side of the interposer exposed. According to the present invention, the molding member of an insulator and the interposer of a semiconductor can be appropriately selected and coupled according to the required fine pitch of a through-hole, and the interposer is molded on substantially the same level as a semiconductor chip, and thus no additional process for embedding the interposer needs to be added.

Abstract translation: 本发明涉及一种嵌入其中的内插器的电路板，包括：插入件，其顶侧和背面通过第一通孔电连接; 以及嵌入在其中并且插入件的顶侧和背面暴露的模制构件。 根据本发明，绝缘体的成型构件和半导体的插入件可以根据通孔的所需精细间距适当地选择和耦合，并且插入器被模制在与半导体芯片基本相同的水平上 ，因此不需要添加用于嵌入插件的附加处理。