公开(公告)号：US20190204586A1

公开(公告)日：2019-07-04

申请号：US16008442

申请日：2018-06-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jose A. MARTINEZ

IPC: G02B26/08 ,  B81C1/00 ,  B81B7/02

CPC classification number: G02B26/0841 ,  B81B7/02 ,  B81B2201/042 ,  B81C1/00047 ,  B81C2201/0132 ,  B81C2201/0133 ,  G09G3/346

Abstract: A microelectromechanical system (MEMS) structure includes at least first and second metal vias. Each of the first and second metal vias includes a respective planar metal layer having a first thickness and a respective post formed from the planar metal layer. The post has a sidewall, and the sidewall has a second thickness greater than 14% of the first thickness.

公开(公告)号：US10071906B2

公开(公告)日：2018-09-11

申请号：US15281589

申请日：2016-09-30

Applicant: INVENSENSE, INC.

Inventor： Michael J. Daneman ,  Fariborz Assaderaghi

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00246 ,  B81B7/0025 ,  B81B7/007 ,  B81B2207/015 ,  B81C1/00531 ,  B81C1/00539 ,  B81C1/00801 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/053 ,  B81C2203/0735

Abstract: Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.

公开(公告)号：US20180237292A1

公开(公告)日：2018-08-23

申请号：US15901196

申请日：2018-02-21

Applicant: Infineon Technologies AG

Inventor： Markus Kahn ,  Anna-Katharina Kaiser ,  Soenke Pirk ,  Juergen Steinbrenner ,  Julia-Magdalena Straeussnigg

IPC: B81C1/00 ,  H04R19/04 ,  H04R19/00

CPC classification number: B81C1/00801 ,  B81C2201/0133 ,  B81C2201/0176 ,  B81C2201/053 ,  B81C2201/056 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00 ,  H04R2201/003

Abstract: A semiconductor device comprises a structured metal layer. The structured metal layer lies above a semiconductor substrate. In addition, a thickness of the structured metal layer is more than 100 nm. Furthermore, the semiconductor device comprises a covering layer. The covering layer lies adjacent to at least one part of a front side of the structured metal layer and adjacent to a side wall of the structured metal layer. In addition, the covering layer comprises amorphous silicon carbide.

公开(公告)号：US20180194616A1

公开(公告)日：2018-07-12

申请号：US15743326

申请日：2016-05-24

Applicant: Robert Bosch GmbH

Inventor： Joerg Muchow ,  Rainer Straub ,  Stefan Pinter

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00103 ,  B81B7/0058 ,  B81B2201/042 ,  B81B2203/0384 ,  B81C1/00317 ,  B81C2201/0133 ,  B81C2201/0143 ,  B81C2201/0154 ,  B81C2203/0136 ,  G02B1/14 ,  G02B26/0833

Abstract: A manufacturing method for a micromechanical window structure including the steps: providing a substrate, the substrate having a front side and a rear side; forming a first recess on the front side; forming a coating on the front side and on the first recess; and forming a second recess on the rear side, so that the coating is at least partially exposed, whereby a window is formed by the exposed area of the coatings.

公开(公告)号：US10017383B2

公开(公告)日：2018-07-10

申请号：US14883825

申请日：2015-10-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Stephen E. Luce ,  Anthony K. Stamper

IPC: B81C1/00 ,  H01H59/00 ,  H01H11/00 ,  H01H49/00 ,  H01H1/58

CPC classification number: B81C1/00698 ,  B81C1/0015 ,  B81C1/00166 ,  B81C1/00523 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0145 ,  B81C2201/0154 ,  B81C2203/0145 ,  H01H1/0036 ,  H01H1/58 ,  H01H11/00 ,  H01H49/00 ,  H01H59/00 ,  H01H59/0009 ,  H01H2059/0018 ,  Y10T29/49105

Abstract: An approach includes a method of fabricating a switch. The approach includes forming a fixed electrode, forming a first cantilevered electrode, forming a second cantilevered electrode aligned vertically over the first fixed electrode, and which has an end that overlaps and is operable to directly contact an end of the first cantilevered electrode upon an application of a voltage to the fixed electrode, and forming a hermetically sealed volume encapsulating the first fixed electrode, the second fixed electrode, the first cantilevered electrode, and the second cantilevered electrode.

公开(公告)号：US20180170745A1

公开(公告)日：2018-06-21

申请号：US15813990

申请日：2017-11-15

Applicant: Infineon Technologies AG

Inventor： Stefan Barzen ,  Wolfgang Friza ,  Marc Fueldner

IPC: B81B3/00 ,  B81C1/00 ,  H04R9/08 ,  H04R31/00

CPC classification number: B81B3/007 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/0361 ,  B81B2203/04 ,  B81C1/00619 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2201/0133 ,  H04R9/08 ,  H04R17/02 ,  H04R19/005 ,  H04R31/00 ,  H04R31/003 ,  H04R2201/003

Abstract: A semiconductor device is proposed. The semiconductor device comprises a membrane structure having an opening. Furthermore, the semiconductor device comprises a first backplate structure, which is arranged on a first side of the membrane structure, and a second backplate structure, which is arranged on a second side of the membrane structure. The semiconductor device furthermore comprises a vertical connection structure, which connects the first backplate structure to the second backplate structure. In this case, the vertical connection structure extends through the opening.

公开(公告)号：US09944518B2

公开(公告)日：2018-04-17

申请号：US14883843

申请日：2015-10-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Stephen E. Luce ,  Anthony K. Stamper

IPC: H01H11/00 ,  H01H49/00 ,  B81C1/00 ,  H01H59/00 ,  H01H1/58

CPC classification number: B81C1/00698 ,  B81C1/0015 ,  B81C1/00166 ,  B81C1/00523 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0145 ,  B81C2201/0154 ,  B81C2203/0145 ,  H01H1/0036 ,  H01H1/58 ,  H01H11/00 ,  H01H49/00 ,  H01H59/00 ,  H01H59/0009 ,  H01H2059/0018 ,  Y10T29/49105

Abstract: An approach includes a method of fabricating a switch. The approach includes forming a first fixed electrode and a second fixed electrode, forming a first cantilevered electrode aligned vertically over the first fixed electrode, forming a second cantilevered electrode aligned vertically over the first fixed electrode and which has an end that overlaps the first cantilevered electrode, forming a third cantilevered electrode aligned vertically over the second fixed electrode and operable to directly contact the first cantilevered electrode upon an application of a voltage to the second fixed electrode, and forming a hermetically sealed volume encapsulating the first fixed electrode, the second fixed electrode, the first cantilevered electrode, and the second cantilevered electrode.

公开(公告)号：US20180016138A1

公开(公告)日：2018-01-18

申请号：US15717234

申请日：2017-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Stephen E. LUCE ,  Anthony K. STAMPER

IPC: B81C1/00 ,  H01H49/00 ,  H01H59/00 ,  H01H11/00 ,  H01H1/58

CPC classification number: B81C1/00698 ,  B81C1/0015 ,  B81C1/00166 ,  B81C1/00523 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0145 ,  B81C2201/0154 ,  B81C2203/0145 ,  H01H1/0036 ,  H01H1/58 ,  H01H11/00 ,  H01H49/00 ,  H01H59/00 ,  H01H59/0009 ,  H01H2059/0018 ,  Y10T29/49105

Abstract: An approach includes a method of fabricating a switch. The approach includes forming a first cantilevered electrode operable to directly contact a second fixed electrode upon an application of a voltage to a first fixed electrode, forming a second cantilevered electrode with an end that overlaps the first cantilevered electrode, and forming a hermetically sealed volume encapsulating the first fixed electrode, the second fixed electrode, the first cantilevered electrode, and the second cantilevered electrode.

公开(公告)号：US20180001582A1

公开(公告)日：2018-01-04

申请号：US15538594

申请日：2015-12-22

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Stephan LANDIS ,  Lamia NOURI

IPC: B29D11/00 ,  G03F7/00 ,  G02B3/02 ,  C23C14/04 ,  B81C1/00 ,  C23C14/58 ,  C23C14/48 ,  H01L21/768 ,  G02B3/00

CPC classification number: B29D11/00365 ,  B81B2203/0376 ,  B81C1/00103 ,  B81C1/0046 ,  B81C99/009 ,  B81C2201/0133 ,  B81C2201/0136 ,  C23C14/042 ,  C23C14/48 ,  C23C14/5853 ,  C23C14/5873 ,  G02B3/0025 ,  G02B3/0031 ,  G02B3/02 ,  G03F7/0002 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76817

Abstract: The invention relates in particular to a method for creating patterns in a layer (410) to be etched, starting from a stack comprising at least the layer (410) to be etched and a masking, layer (420) on top of the layer (410) to be etched, the masking layer (420) having at least one pattern (421), the method comprising at least; a) a step of modifying at least one zone (411) of the layer (410) to be etched via ion implantation (430) vertically in line with said at least one pattern (421); b) at least one sequence of steps comprising: b1) a step of enlarging (440) the at least one pattern (421) in a plane in which the layer (410) to be etched mainly extends; b2) a step of modifying at least one zone (411″, 411″) of the layer (410) to be etched via ion implantation (430) vertically in line with the at least one enlarged pattern (421), the implantation being carried out over a depth less than the implantation depth of the preceding, modification step;) c) a step of removing (461, 462) the modified zones (411, 411′, 41″), the removal comprising a step of etching the modified zones (411, 411′, 411″) selectively with respect to the non-modified zones (412) of the layer (410) to be etched.

公开(公告)号：US20170374729A1

公开(公告)日：2017-12-28

申请号：US15700937

申请日：2017-09-11

Applicant: Honeywell International Inc.

Inventor： James Goeders ,  Matthew S. Marcus ,  Thomas Ohnstein ,  Terry Dean Stark

IPC: H05H3/02 ,  B81B7/02 ,  B81C1/00

CPC classification number: H05H3/02 ,  B81B7/02 ,  B81B2203/0127 ,  B81C1/00158 ,  B81C2201/0132 ,  B81C2201/0133

Abstract: A micro-structured atomic source system is described herein. One system includes a silicon substrate, a dielectric diaphragm, wherein the dielectric diaphragm includes a heater configured to heat an atomic source substance, an intermediary material comprising a chamber configured to receive the atomic source substance, and a guide material configured to direct a flux of atoms from the atomic source substance.