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    Protective Coating on Trench Features of a Wafer and Method of Fabrication Thereof
    113.
    发明申请
    Protective Coating on Trench Features of a Wafer and Method of Fabrication Thereof 有权

    公开(公告)号：US20180002165A1

    公开(公告)日：2018-01-04

    申请号：US15196395

    申请日：2016-06-29

    Applicant: Akustica, Inc. ,  Robert Bosch GmbH

    Inventor： Mikko VA Suvanto

    IPC: B81B7/00 ,  B81C1/00 ,  H01L23/00

    CPC classification number: B81B7/0058 ,  B81B2203/033 ,  B81C1/00404 ,  B81C1/00825 ,  B81C1/00896 ,  B81C2201/053 ,  H01L21/78 ,  H01L23/562

    Abstract: A coating for protecting a wafer from moisture and debris due to dicing, singulating, or handling the wafer is provided. A semiconductor sensor device comprises a wafer having a surface and at least one trench feature and the protective coating covering the trench feature. The trench feature comprises a plurality of walls and the walls are covered with the protective coating, wherein the walls of the trench feature are formed as a portion of the semiconductor sensor device. The semiconductor sensor device further comprises a patterned mask formed on the wafer before the trench feature is formed, wherein the protective coating is formed directly to the trench feature and the patterned mask. The semiconductor sensor device is selected from a group consisting of a MEMS die, a sensor die, a sensor circuit die, a circuit die, a pressure die, an accelerometer, a gyroscope, a microphone, a speaker, a transducer, an optical sensor, a gas sensor, a bolometer, a giant megnetoresistive sensor (GMR), a tunnel magnetoresistive (TMR) sensor, an environmental sensor, and a temperature sensor.

    Integrated MEMS device
    115.
    发明授权
    Integrated MEMS device 有权

    公开(公告)号：US09676609B2

    公开(公告)日：2017-06-13

    申请号：US15144896

    申请日：2016-05-03

    Applicant: Asia Pacific Microsystems, Inc.

    Inventor： Jerwei Hsieh

    IPC: H01L21/4763 ,  B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/0038 ,  B81B7/0058 ,  B81B2201/032 ,  B81C1/00238 ,  B81C1/00817 ,  B81C1/00825 ,  B81C2201/053 ,  B81C2201/056 ,  B81C2203/0785

    Abstract: An integrated MEMS device is provided. The integrated MEMS device comprises a circuit chip and a device chip. The circuit chip has a patterned first bonding layer disposed thereon, the bonding layer being composed of a conductive material/materials. The device chip has a first structural layer and a second structural layer, the first structural layer being connected to the second structural layer and the first bonding layer of the circuit chip, and being sandwiched between the second structural layer and the circuit chip. A plurality of hermetic spaces are enclosed by the first structural layer, the second structural layer, the first bonding layer and the circuit chip.

    COMPOSITE CAVITY AND FORMING METHOD THEREOF
    118.
    发明申请
    COMPOSITE CAVITY AND FORMING METHOD THEREOF 审中-公开
    复合孔及其形成方法

    公开(公告)号：US20170044006A1

    公开(公告)日：2017-02-16

    申请号：US15305799

    申请日：2014-11-05

    Applicant: ADVANCED SEMICONDUCTOR MANUFACTURING CO. LTD

    Inventor： Yuanjun Xu ,  Yilin Yan ,  Weijia Xue

    IPC: B81B7/02 ,  B81C1/00

    CPC classification number: B81B7/02 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00158 ,  B81C1/00396 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/019 ,  B81C2201/0198 ,  B81C2201/053

    Abstract: There is provided a method for forming a composite cavity and a composite cavity formed using the method. The method comprises the following steps: providing a silicon substrate (101); forming an oxide layer on the front side thereof; patterning the oxide layer to form one or more grooves (103), the position of the groove (103) corresponding to the position of small cavity (109) to be formed; providing a bonding wafer (104), which is bonded to the patterned oxide layer to form one or more closed micro-cavity structures (105) between the silicon substrate (101) and the bonding wafer (104); forming a protective film (106) over the bonding wafer (104) and forming a masking layer (107) on the back side of the silicon substrate (101); patterning the masking layer (107), the pattern of the masking layer (107) corresponding to the position of a large cavity (108) to be formed; using the masking layer (107) as a mask, etching the silicon substrate (101) from the back side until the oxide layer at the front side thereof to form the large cavity (108) in the silicon substrate (101); and using the masking layer (107) and the oxide layer as a mask, etching the bonding wafer (104) from the back side through the silicon substrate (101) until the protective film (106) thereover to form one or more small cavities (109) in the bonding wafer (104). The uniformity of thickness of the semiconductor medium layer where the small cavity (109) in the composite cavity is located is well controlled by the present invention.

    Abstract translation: 提供了使用该方法形成复合腔和复合腔的方法。 该方法包括以下步骤：提供硅衬底（101）; 在其前侧形成氧化物层; 图案化氧化物层以形成一个或多个凹槽（103），凹槽（103）的位置对应于待形成的小空腔（109）的位置; 提供接合晶片（104），其接合到所述图案化氧化物层以在所述硅衬底（101）和所述接合晶片（104）之间形成一个或多个闭合微腔结构（105）; 在所述接合晶片（104）上形成保护膜（106），并在所述硅衬底（101）的背侧上形成掩模层（107）; 图案化掩模层（107），对应于待形成的大空腔（108）的位置的掩模层（107）的图案; 使用掩模层（107）作为掩模，从背面蚀刻硅衬底（101）直到其前侧的氧化物层在硅衬底（101）中形成大空腔（108）; 并且使用所述掩模层（107）和所述氧化物层作为掩模，通过所述硅衬底（101）从所述背面蚀刻所述接合晶片（104）直到所述保护膜（106）在其上形成一个或多个小空腔 109）。 复合空腔中的小空腔（109）所在的半导体介质层的厚度均匀性由本发明很好地控制。

    CMOS-MEMS integrated device with selective bond pad protection
    119.
    发明授权
    CMOS-MEMS integrated device with selective bond pad protection 有权
    CMOS-MEMS集成器件，具有选择性接合焊盘保护

    公开(公告)号：US09505609B2

    公开(公告)日：2016-11-29

    申请号：US14699938

    申请日：2015-04-29

    Applicant: InvenSense, Inc.

    Inventor： Daesung Lee

    IPC: B81C1/00

    CPC classification number: B81C1/00801 ,  B81B7/0025 ,  B81B2207/07 ,  B81C2201/053 ,  B81C2203/0785

    Abstract: A method and system for preparing a semiconductor wafer are disclosed. In a first aspect, the method comprises providing a passivation layer over a patterned top metal on the semiconductor wafer, etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask, depositing a protection layer on the semiconductor wafer, patterning the protective layer using a second mask, and etching the passivation layer to open other electrodes in the semiconductor wafer using a third mask. The system comprises a MEMS device that further comprises a first substrate and a second substrate bonded to the first substrate, wherein the second substrate is prepared by the aforementioned steps of the method.

    Abstract translation: 公开了一种用于制备半导体晶片的方法和系统。 在第一方面，该方法包括在半导体晶片上的图案化的顶部金属上提供钝化层，蚀刻钝化层以使用第一掩模打开半导体晶片中的接合焊盘，在半导体晶片上沉积保护层，图案化 使用第二掩模的保护层，并且使用第三掩模蚀刻钝化层以打开半导体晶片中的其它电极。 该系统包括MEMS器件，其还包括第一基底和与第一基底结合的第二基底，其中第二基底是通过上述方法的步骤制备的。

    SUPPORT PILLAR
    120.
    发明申请
    SUPPORT PILLAR 审中-公开
    支撑支柱

    公开(公告)号：US20160332865A1

    公开(公告)日：2016-11-17

    申请号：US15155448

    申请日：2016-05-16

    Applicant: Foresee Technology Corp.

    Inventor： Chien-Chan CHEN ,  Yi-Der LIANG ,  Shiao-Yi LIN ,  Cheng-Kuang YANG

    IPC: B81B3/00 ,  H04R19/00 ,  H04R19/04 ,  B81C1/00

    CPC classification number: B81B3/0054 ,  B81B2201/0257 ,  B81B2203/0118 ,  B81B2203/0361 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/013 ,  B81C2201/053 ,  B81C2203/0714 ,  B81C2203/0735 ,  H04R19/005 ,  H04R19/04

    Abstract: A support pillar is formed under a movable film for support. The support pillar includes a plurality of first metal micropillars, a base metal connection pillar layer and a first oxide encapsulation layer. The first metal micropillars are formed under the movable film and conductively connected to the movable film via metal connection. The base metal connection pillar layer is formed under the first metal micropillars and conductively connected to the first metal micropillars. The first oxide encapsulation layer fully or partially encapsulates the first metal micropillars to insulate the first metal micropillars from air, and shape the support pillar into a column shape.

    Abstract translation: 支撑柱形成在用于支撑的可移动膜下。 支撑柱包括多个第一金属微柱，贱金属连接柱层和第一氧化物封装层。 第一金属微透镜形成在可动膜下方，并通过金属连接导电地连接到可动膜上。 基底金属连接柱层形成在第一金属微柱下面，并与第一金属微柱导电连接。 第一氧化物封装层完全或部分地封装第一金属微柱，以将第一金属微柱与空气绝缘，并将支柱形成柱形。

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