公开(公告)号：US20110063811A1

公开(公告)日：2011-03-17

申请号：US12948894

申请日：2010-11-18

Applicant: Takashi KARIYA ,  Akira Mochida

Inventor： Takashi KARIYA ,  Akira Mochida

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A printed wiring board includes a main body having a mounting portion and ground and power supply pads in the mounting portion such that a ground line of a semiconductor device is connected to a ground pad and a power supply line of the device is connected to a power supply pad, and a layered capacitor disposed in the main body and having a high dielectric constant layer and first and second layer electrodes sandwiching the dielectric layer. One of the electrodes is connected to the power supply line and the other electrode is connected to the ground line, the first electrode has a solid pattern including passage holes through which second rod terminals connected to the second electrode pass in a non-contacting manner, and the second electrode has a solid pattern including passage holes through which first rod terminals connected to the first electrode pass in a non-contacting manner.

Abstract translation: 一种印刷电路板，包括具有安装部分的主体和安装部分中的接地和电源焊盘，使得半导体器件的接地线连接到接地焊盘，并且该设备的电源线连接到电源 供电焊盘和设置在主体中并具有高介电常数层的层状电容器和夹着介电层的第一和第二层电极。 电极中的一个连接到电源线，另一个电极连接到接地线，第一电极具有固体图案，其包括通孔，第二电极与第二电极连接，第二电极以非接触的方式通过， 并且第二电极具有固体图案，其包括通孔，通过该通孔与第一电极连接的第一杆端子以非接触方式通过。

公开(公告)号：US07786002B2

公开(公告)日：2010-08-31

申请号：US10515035

申请日：2003-05-23

Applicant: Jürgen Leib ,  Dietrich Mund

Inventor： Jürgen Leib ,  Dietrich Mund

IPC: H01L21/4763

CPC classification number: C03B19/00 ,  C03C3/083 ,  C03C3/089 ,  C03C4/12 ,  C03C14/006 ,  C03C15/00 ,  C03C17/02 ,  C03C17/34 ,  C03C2214/16 ,  C03C2217/21 ,  C03C2217/77 ,  C03C2218/15 ,  C03C2218/32 ,  C03C2218/328 ,  C03C2218/33 ,  C03C2218/355 ,  C23C14/10 ,  H01L21/02129 ,  H01L21/02145 ,  H01L21/02161 ,  H01L21/02263 ,  H01L21/31616 ,  H01L21/31625 ,  H01L21/50 ,  H01L21/56 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76885 ,  H01L23/10 ,  H01L23/291 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49894 ,  H01L23/66 ,  H01L24/97 ,  H01L51/5203 ,  H01L51/5237 ,  H01L51/5262 ,  H01L2223/6627 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1903 ,  H01L2924/19033 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H01P3/003 ,  H01P11/003 ,  H05K3/28 ,  H05K3/467 ,  H05K2201/0179 ,  Y02P40/57 ,  H01L2924/00

Abstract: The invention provides a process for producing a substrate having a conductor arrangement that is suitable for radio-frequency applications, with improved radio-frequency properties. For this purpose, the process includes the steps of: depositing a structured glass layer having at least one opening over a contact-connection region by evaporation coating on the substrate and applying at least one conductor structure to the structured glass layer so that the at least one conductor has electrical contact with the contact-connection region.

Abstract translation: 本发明提供一种制造具有适用于射频应用的导体装置的基板的方法，具有改进的射频特性。 为此，该方法包括以下步骤：在衬底上沉积通过蒸发涂层在接触连接区域上具有至少一个开口的结构化玻璃层，并将至少一个导体结构施加到结构化玻璃层，使得至少 一个导体与接触连接区域电接触。

公开(公告)号：US20100159193A1

公开(公告)日：2010-06-24

申请号：US12338283

申请日：2008-12-18

Applicant: Michael Y. Young ,  Patrick C. Cheung ,  Stephen David White ,  John R. Andrews ,  David J. Gervasi

Inventor： Michael Y. Young ,  Patrick C. Cheung ,  Stephen David White ,  John R. Andrews ,  David J. Gervasi

IPC: B32B3/24

CPC classification number: B41J2/14233 ,  H05K1/0272 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/429 ,  H05K2201/0179 ,  H05K2201/09581 ,  H05K2201/09809 ,  H05K2203/0315 ,  Y10T428/24322

Abstract: A via structure configured for electrical and fluidic interconnection, and including an electrically conductive layer and an electrically insulating layer disposed on the electrically conductive layer.

Abstract translation: 导电结构，其被配置用于电和流体互连，并且包括设置在所述导电层上的导电层和电绝缘层。

公开(公告)号：US07683740B2

公开(公告)日：2010-03-23

申请号：US11878452

申请日：2007-07-24

Applicant: Toshiyuki Yoshizawa ,  Masahiro Miyazaki ,  Akira Furuya ,  Masaomi Ishikura ,  Hajime Kuwajima

Inventor： Toshiyuki Yoshizawa ,  Masahiro Miyazaki ,  Akira Furuya ,  Masaomi Ishikura ,  Hajime Kuwajima

IPC: H03H7/01

CPC classification number: H05K1/162 ,  H01L27/016 ,  H01L28/10 ,  H01L28/40 ,  H05K1/165 ,  H05K3/0023 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/1006

Abstract: An electronic component having: a substrate, a lower conductor layer provided on the substrate; an inorganic dielectric film that covers the lower conductor layer; and an upper conductor layer having an upper electrode portion provided on the inorganic dielectric film. The lower conductor layer has a lower electrode portion that together with the upper electrode portion and the inorganic dielectric film constitutes a capacitor, and a coil portion that constitutes an inductor. The entire inorganic dielectric film is formed integrally, and the lower conductor layer is in contact only with the substrate, inorganic dielectric film, and upper conductor layer.

Abstract translation: 一种电子部件，具有：基板，设置在基板上的下导体层; 覆盖下导体层的无机介电膜; 以及具有设置在无机介电膜上的上电极部的上导体层。 下导体层具有与上部电极部分和无机电介质膜一起构成电容器的下部电极部分和构成电感器的线圈部分。 整个无机介电膜一体形成，下导体层仅与基板，无机介电膜和上导体层接触。

公开(公告)号：US20090291200A1

公开(公告)日：2009-11-26

申请号：US12533503

申请日：2009-07-31

Applicant: John M. Bedinger ,  Michael A. Moore

Inventor： John M. Bedinger ,  Michael A. Moore

IPC: B05D5/12

CPC classification number: H05K3/284 ,  H01L23/3192 ,  H01L23/4821 ,  H01L24/83 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/8592 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2203/1322 ,  Y10T29/49124 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49982 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29075 ,  H01L2924/00014

Abstract: A method includes providing a circuit board having an outer surface, the outer surface configured with a plurality of discrete electrical components that are each manufactured independently of one another, and coating the outer surface and the plurality of discrete electrical components with a first protective dielectric layer. The method further includes coating the first protective dielectric layer with a second dielectric layer. The second dielectric layer includes a dielectric material having a modulus of elasticity less than 3.5 Giga-Pascal (GPa), a dielectric constant less than 2.7, a dielectric loss less than 0.002, a breakdown voltage strength in excess of 2 million volts/centimeter (MV/cm), a temperature stability to 3000 Celsius, a defect densities less than 0.5/centimeter, a pinhole free in films greater than 50 Angstroms, and is capable of being deposited conformally over and under 3D structures with thickness uniformity less than or equal to 10%.

Abstract translation: 一种方法包括提供具有外表面的电路板，所述外表面被配置有彼此独立制造的多个分立电气部件，并且用第一保护介电层涂覆所述外表面和所述多个分立的电部件 。 该方法还包括用第二介电层涂覆第一保护介电层。 第二电介质层包括弹性模量小于3.5千兆帕（GPa），介电常数小于2.7的介电材料，介电损耗小于0.002，击穿电压强度超过2百万伏/厘米（ MV / cm），温度稳定度为3000摄氏度，缺陷密度小于0.5 /厘米，薄膜中大小不超过50埃的针孔，并且能够在厚度均匀度小于或等于3维的3D结构下保形地沉积 至10％。

公开(公告)号：US07614142B2

公开(公告)日：2009-11-10

申请号：US12068272

申请日：2008-02-05

Applicant: Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

Inventor： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

IPC: H05K3/36 ,  H01L23/29

CPC classification number: H01L23/50 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/0044 ,  H05K3/20 ,  H05K3/4614 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0733 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599

Abstract: A method for fabricating an interposer includes: forming on one primary surface of a first substrate a thin-film capacitor including a first capacitor electrode, a crystalline capacitor dielectric film formed on the first electrode and a second capacitor electrode formed on the dielectric film; and forming on the primary surface of the first substrate and the capacitor a first layer as semi-cured, and a first partial electrode to be a part of a through-electrode, buried in the first resin layer and electrically connected to the first electrode or the second electrode. The method further includes cutting an upper part of the first partial electrode and an upper part of the first resin layer with a cutting tool; forming on one primary surface of a second substrate a second resin layer as semi-cured, and a second partial electrode to be a part of the through-electrode, buried in the second resin layer and disposed in alignment with the first partial electrode; cutting an upper part of the second partial electrode and an upper part of the second resin layer with a cutting tool; making thermal processing with the first resin layer and the second resin layer in close contact with each other to adhere the first resin and the second resin layer to each other while jointing the first and second partial electrodes to each other; removing the first substrate; forming on said one primary surface of the second substrate a third resin layer, covering the thin-film capacitor, burying a third partial electrode to be a part of the through-electrode in the third resin layer, supporting the third resin layer by a supporting substrate; and removing the second substrate.

Abstract translation: 一种用于制造插入件的方法，包括：在第一基板的一个主表面上形成薄膜电容器，薄膜电容器包括第一电容器电极，形成在第一电极上的晶体电容器电介质膜和形成在电介质膜上的第二电容器电极; 并且在第一基板和电容器的主表面上形成半固化的第一层，以及作为通孔的一部分的第一部分电极，埋入第一树脂层中并电连接到第一电极或 第二电极。 该方法还包括用切割工具切割第一部分电极的上部和第一树脂层的上部; 在第二基板的一个主表面上形成半固化的第二树脂层和作为所述通孔的一部分的第二部分电极，所述第二部分电极埋入所述第二树脂层中并与所述第一部分电极对准; 用切割工具切割第二部分电极的上部和第二树脂层的上部; 使第一树脂层和第二树脂层彼此紧密接触进行热处理，以将第一和第二部分电极彼此接合，使第一树脂和第二树脂层彼此粘合; 去除第一衬底; 在所述第二基板的所述一个主表面上形成覆盖所述薄膜电容器的第三树脂层，在所述第三树脂层中埋设作为所述贯通电极的一部分的第三部分电极，通过支撑所述第三树脂层 基质; 并移除第二基板。

公开(公告)号：US20090250248A1

公开(公告)日：2009-10-08

申请号：US12219708

申请日：2008-07-28

Applicant: Ming-Chi Kan ,  Shao-Chung Hu

Inventor： Ming-Chi Kan ,  Shao-Chung Hu

IPC: H05K3/44 ,  H05K1/05

CPC classification number: H05K1/053 ,  H01L23/3735 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/73265 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/0323 ,  Y10T29/49155 ,  H01L2924/00014

Abstract: A support substrate structure for supporting an electronic component thereon comprises a thermal conductive substrate, a first ceramic layer, an insulating thermal conductive layer and a conductive pattern. The thermal conductive substrate has an upper surface and a lower surface; the first ceramic layer is disposed on the upper surface of the thermal conductive substrate; the insulating thermal conductive layer is disposed on the first ceramic layer; and the conductive pattern is formed on a surface of the insulating thermal conductive layer. The present invention also discloses a method for fabricating the aforementioned support substrate structure.

Abstract translation: 用于在其上支撑电子部件的支撑基板结构包括导热基板，第一陶瓷层，绝缘导热层和导电图案。 导热基板具有上表面和下表面; 第一陶瓷层设置在导热基板的上表面上; 绝缘导热层设置在第一陶瓷层上; 并且导电图案形成在绝缘导热层的表面上。 本发明还公开了一种用于制造上述支撑衬底结构的方法。

公开(公告)号：US07588992B2

公开(公告)日：2009-09-15

申请号：US11152328

申请日：2005-06-14

Applicant: Yongki Min

Inventor： Yongki Min

IPC: H01L21/461

CPC classification number: H01L27/016 ,  H01L21/4857 ,  H01L23/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/16152 ,  H05K1/162 ,  H05K3/025 ,  H05K3/4652 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2203/0384 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A thin-film capacitor assembly includes a first metal bottom electrode, a dielectric layer, a second metal etch-stop layer, and a subsequent metal top electrode. The first metal bottom electrode is in contact with the dielectric layer. The second metal etch-stop layer is in contact with the dielectric layer. The subsequent metal top electrode is in contact with the second metal etch-stop layer. Processing of the thin-film capacitor assembly includes totally removing a stiffener after assembling the first metal bottom electrode as a layer to the dielectric layer and the second metal etch-stop layer. The stiffener is removed from above and on the second metal etch-stop layer. The thin-film capacitor assembly is laminated to a mounting substrate.

Abstract translation: 薄膜电容器组件包括第一金属底电极，电介质层，第二金属蚀刻停止层和随后的金属顶电极。 第一金属底电极与电介质层接触。 第二金属蚀刻停止层与电介质层接触。 随后的金属顶电极与第二金属蚀刻停止层接触。 薄膜电容器组件的处理包括在将第一金属底电极组装成介电层和第二金属蚀刻停止层之后，完全去除加强件。 加强件从第二金属蚀刻停止层上方和第二金属蚀刻停止层移除。 将薄膜电容器组件层压到安装基板上。

公开(公告)号：US20090208640A1

公开(公告)日：2009-08-20

申请号：US12432221

申请日：2009-04-29

Applicant: Won Hoon SONG ,  Yul Kyo Chung ,  Sung Taek Lim

Inventor： Won Hoon SONG ,  Yul Kyo Chung ,  Sung Taek Lim

IPC: B05D5/12 ,  C23C14/34

CPC classification number: H01L21/02197 ,  H01G4/33 ,  H01L21/02186 ,  H01L21/02282 ,  H01L21/31683 ,  H01L21/31691 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179

Abstract: The invention relates to a fabrication method of a composite metal oxide dielectric film containing at least two metallic elements on a substrate, and a composite metal oxide dielectric film fabricated thereby. The method includes: forming an amorphous film containing at least one of the metallic elements; preparing a hydrothermal solution where a precursor of the remaining element of the metallic elements is mixed; immersing the amorphous film into the hydrothermal solution; and hydrothermally treating the amorphous film so that the remaining one of the metallic elements is synthesized to the amorphous film, thereby forming a crystallized composite metal oxide film.

Abstract translation: 本发明涉及在基板上含有至少两种金属元素的复合金属氧化物电介质膜的制造方法以及由此制造的复合金属氧化物电介质膜。 该方法包括：形成含有至少一种金属元素的非晶膜; 制备其中混合金属元素的剩余元素的前体的水热溶液; 将非晶膜浸入水热溶液中; 对该非晶质膜进行水热处理，使残留的金属元素与非晶质膜合成，从而形成结晶化复合金属氧化物膜。

公开(公告)号：US20090205858A1

公开(公告)日：2009-08-20

申请号：US12314086

申请日：2008-12-03

Applicant: Bernd Haegele

Inventor： Bernd Haegele

IPC: H05K1/18 ,  B05D5/12 ,  B05D3/00

CPC classification number: H05K1/053 ,  C03C3/064 ,  C23C4/18 ,  H05K1/092 ,  H05K2201/0116 ,  H05K2201/017 ,  H05K2201/0179 ,  H05K2203/1147 ,  H05K2203/1366 ,  Y10T29/49126 ,  Y10T29/49146

Abstract: Circuit carrier having a metal support layer, at least some portions of which are covered by a dielectric layer, the latter having a plurality of pores, with the pores being sealed by glass at least on the opposite side of the dielectric layer to the support layer.

Abstract translation: 具有金属支撑层的电路载体，其至少一些部分被电介质层覆盖，该电介质层具有多个孔，孔至少在电介质层的与支撑层相反的一侧被玻璃密封 。