公开(公告)号：US09232639B2

公开(公告)日：2016-01-05

申请号：US13707113

申请日：2012-12-06

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tao Wu ,  Zhiguo Qian ,  Kemal Aygun

IPC: H05K7/10 ,  H05K1/02 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K1/0298 ,  H01L21/4846 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described.

Abstract translation: 本文描述的一些实施例包括形成这种装置的装置和方法。 一个这样的实施例可以包括具有要耦合到半导体管芯的焊盘的布线布置，其中第一迹线耦合到焊盘之间的第一焊盘，以及耦合到焊盘之间的第二焊盘的第二迹线。 第一和第二迹线可以具有不同的厚度。 描述包括附加装置和方法的其他实施例。

公开(公告)号：US20150131254A1

公开(公告)日：2015-05-14

申请号：US14228250

申请日：2014-03-28

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Min-Sung KIM ,  Jun-Hyung SON

IPC: H05K1/02 ,  H05K3/18 ,  H05K3/46 ,  H05K3/06 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0271 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/111 ,  H05K3/06 ,  H05K3/108 ,  H05K3/3436 ,  H05K3/4682 ,  H05K2201/0352 ,  H05K2201/09136 ,  H05K2201/094 ,  H05K2201/09736 ,  H05K2201/09972 ,  H05K2201/10674 ,  H05K2203/0353 ,  H05K2203/0574 ,  H05K2203/302 ,  Y02P70/611

Abstract: The present invention discloses a printed circuit board, a semiconductor package having the same, and a method for manufacturing the same. A printed circuit board according to an aspect of the present invention includes: a package board including a mounting area and a peripheral area, the mounting area having a semiconductor chip mounted therein, the peripheral area surrounding the mounting area; a first central circuit pattern formed in the mounting area on one surface of the package board; a second central circuit pattern formed in the mounting area on the other surface of the package board and having a greater thickness than the first central circuit pattern; a first peripheral circuit pattern formed in the peripheral area on the one surface of the package board; and a second peripheral circuit pattern formed in the peripheral area on the other surface of the package board and having a greater thickness than the second peripheral circuit pattern.

Abstract translation: 本发明公开了一种印刷电路板，具有该印刷电路板的半导体封装及其制造方法。 根据本发明的一个方面的印刷电路板包括：包括安装区域和周边区域的封装板，安装区域具有安装在其中的半导体芯片，围绕安装区域的周边区域; 形成在所述封装板的一个表面上的所述安装区域中的第一中心电路图案; 形成在所述封装板的另一表面上的所述安装区域中并且具有比所述第一中心电路图案更大的厚度的第二中心电路图案; 形成在所述封装板的一个表面上的周边区域中的第一外围电路图案; 以及第二外围电路图案，其形成在所述封装板的另一表面的周边区域中，并且具有比所述第二外围电路图案更大的厚度。

公开(公告)号：US20150062851A1

公开(公告)日：2015-03-05

申请号：US14469782

申请日：2014-08-27

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Wataru KANEDA ,  Hiromu ARISAKA ,  Akio ROKUGAWA

IPC: H05K1/11 ,  H05K1/09 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K3/421 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/115 ,  H05K1/116 ,  H05K3/38 ,  H05K3/4644 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/09381 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/2072 ,  H05K2203/0789 ,  H01L2924/00

Abstract: A wiring board includes a first insulating layer coating a first wiring layer. A first through hole is opened in a surface of the first insulating layer and exposes a surface of the first wiring layer. A first via arranged in the first through hole includes an end surface exposed to the surface of the first insulating layer. A gap is formed between the first insulating layer and the first via in the first through hole. A second wiring layer is stacked on the surface of the first insulating layer and the end surface of the first via. The second wiring layer includes a pad filling the gap. The pad is greater in planar shape than the first through hole.

Abstract translation: 布线板包括涂覆第一布线层的第一绝缘层。 第一通孔在第一绝缘层的表面上开放，并露出第一布线层的表面。 布置在第一通孔中的第一通孔包括暴露于第一绝缘层的表面的端表面。 在第一通孔中的第一绝缘层和第一通孔之间形成间隙。 在第一绝缘层的表面和第一通孔的端面上堆叠第二布线层。 第二布线层包括填充间隙的垫。 该垫的平面形状大于第一通孔。

公开(公告)号：US20150008018A1

公开(公告)日：2015-01-08

申请号：US14317498

申请日：2014-06-27

Applicant: FUJITSU LIMITED

Inventor： Shunji Baba ,  TAKASHI KANDA

IPC: H05K1/02

CPC classification number: H05K3/4694 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/14 ,  H05K2201/0352 ,  H05K2203/061

Abstract: A multilayer substrate includes a first substrate a second substrate that is stacked on and electrically connected to the first substrate, the second substrate having a different characteristic from a characteristic of the first substrate, a third substrate that is provided on a side of the first substrate, the second substrate being provided on the side of the first substrate, and the third substrate is electrically connected to the second substrate, and a connection member that electrically connects the first substrate and the third substrate to each other while the second substrate is bypassed.

Abstract translation: 多层基板包括第一基板和第二基板，第二基板层叠并电连接到第一基板，第二基板具有与第一基板的特性不同的特性，第三基板设置在第一基板的一侧 所述第二基板设置在所述第一基板的一侧，并且所述第三基板电连接到所述第二基板，以及连接构件，其在所述第二基板旁路的同时使所述第一基板和所述第三基板彼此电连接。

公开(公告)号：US08813353B2

公开(公告)日：2014-08-26

申请号：US12785037

申请日：2010-05-21

Applicant: Yasuhiko Inui ,  Takamichi Ogawa ,  Seiji Ichiyanagi ,  Jun Otsuka ,  Manabu Sato

Inventor： Yasuhiko Inui ,  Takamichi Ogawa ,  Seiji Ichiyanagi ,  Jun Otsuka ,  Manabu Sato

IPC: H05K3/20 ,  H01L23/498 ,  H05K1/16 ,  H01L23/50 ,  H01L21/48 ,  H05K1/09 ,  H05K3/46

CPC classification number: H05K1/162 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/092 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09736 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/4981 ,  Y10T407/1946 ,  Y10T407/1948 ,  H01L2924/00

Abstract: A dielectric structure including a metal foil, a dielectric layer and a conductor layer provided in this order, wherein the metal foil has a thickness of from 10 to 40 μm, the dielectric layer has a thickness of from 0.3 to 5 μm, and the conductor layer has a thickness of from 0.3 to 10 μm. The dielectric structure has plural vias which are separated from each other, and which penetrate through both of the dielectric layer and the conductor layer. The vias of the dielectric layer have different diameters which are in a range of from 100 to 300 μm, a diameter of each of the vias of the conductor layer is larger than a diameter of a corresponding via of the dielectric layer by 5 to 50 μm, and a minimum via pitch is from 100 to 350 μm.

Abstract translation: 包括依次设置的金属箔，电介质层和导体层的电介质结构体，其中金属箔的厚度为10〜40μm，电介质层的厚度为0.3〜5μm，导体 层的厚度为0.3〜10μm。 电介质结构具有彼此分离并且穿透介电层和导体层两者的多个通孔。 电介质层的通孔具有不同的直径，范围为100〜300μm，导体层的通孔的直径大于电介质层的通孔的直径为5〜50μm ，最小通孔间距为100〜350μm。

公开(公告)号：US20140226296A1

公开(公告)日：2014-08-14

申请号：US14129399

申请日：2012-02-10

Applicant: KABUSHIKI KAISHA TOYOTA , JIDOSHOKKI

Inventor： Hiroaki Asano ,  Yasuhiro Koike ,  Kiminori Ozaki ,  Hitoshi Shimadu ,  Tetsuya Furuta ,  Masao Miyake ,  Takahiro Hayakawa ,  Tomoaki Asai ,  Ryou Yamauchi

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0263 ,  H05K1/0206 ,  H05K1/0265 ,  H05K1/18 ,  H05K3/202 ,  H05K3/4092 ,  H05K3/46 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0397 ,  H05K2201/10166 ,  H05K2201/10409 ,  H05K2203/0195

Abstract: This multi-layer wiring board is provided with an insulating substrate, an inner layer copper sheet, and an outer layer copper foil. The inner layer copper sheet is disposed within the insulating substrate and has been patterned. The outer layer copper foil is disposed in a state of having been patterned at the surface of the insulating substrate, is thinner than the inner layer copper sheet, and has a cross-sectional area of the current path that is smaller than the cross-sectional area of the current path of the inner layer copper sheet. As a result, provided are: a multi-layer wiring board that can flow a large current and a smaller current while suppressing an increase in the projected area of the substrate; and a method for producing the multi-layer wiring board.

Abstract translation: 该多层布线板设置有绝缘基板，内层铜板和外层铜箔。 内层铜片设置在绝缘基板内并被图案化。 外层铜箔被设置在绝缘基板的表面被图案化的状态下，比内层铜片薄，并且具有小于横截面的电流路径的截面积 内层铜片电流通路面积。 结果，提供了：能够抑制基板的投影面积的增加而能够流过大电流和小电流的多层布线基板; 以及多层布线基板的制造方法。

公开(公告)号：US08796848B2

公开(公告)日：2014-08-05

申请号：US13004242

申请日：2011-01-11

Applicant: Wen-Yuan Chang ,  Wei-Cheng Chen ,  Yeh-Chi Hsu

Inventor： Wen-Yuan Chang ,  Wei-Cheng Chen ,  Yeh-Chi Hsu

IPC: H01L23/498 ,  H05K3/24 ,  H01L23/00 ,  H05K3/46 ,  H05K3/40 ,  H05K3/28

CPC classification number: H05K3/242 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2203/054 ,  H05K2203/0723 ,  H01L2224/05099

Abstract: A circuit board includes a substrate that has a top surface and a base surface opposite to each other, at least a top pad disposed on the top surface, a top solder resist layer disposed on the top surface and covering a portion of the top pad, and a pre-bump disposed on the top pad. The top solder resist layer has a first opening exposing a portion of the top pad. The pre-bump is located in the first opening and has a protrusion protruding from the top solder resist layer. A maximum width of the protrusion is less than or equal to a width of the top pad. A chip package structure having the circuit board is also provided.

Abstract translation: 电路板包括具有彼此相对的顶表面和底表面的基底，至少设置在顶表面上的顶垫，设置在顶表面上并覆盖顶垫的一部分的顶部阻焊层， 以及设置在顶垫上的预凸块。 顶部阻焊层具有暴露顶部焊盘的一部分的第一开口。 预凸块位于第一开口中并且具有从顶部阻焊层突出的突起。 突起的最大宽度小于或等于顶垫的宽度。 还提供了具有电路板的芯片封装结构。

公开(公告)号：US08742262B2

公开(公告)日：2014-06-03

申请号：US13483837

申请日：2012-05-30

Applicant: Scott E. Gordon ,  Elizabeth D. Hughes ,  Joao Carlos Malerbi ,  Deepukumar M. Nair ,  Kumaran Manikantan Nair ,  James M. Parisi ,  Michael Arnett Smith ,  Ken E. Souders

Inventor： Scott E. Gordon ,  Elizabeth D. Hughes ,  Joao Carlos Malerbi ,  Deepukumar M. Nair ,  Kumaran Manikantan Nair ,  James M. Parisi ,  Michael Arnett Smith ,  Ken E. Souders

IPC: H05K1/09 ,  H05K1/00 ,  H05K1/03 ,  H05K3/02 ,  B05D5/12

CPC classification number: H01L23/15 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/165 ,  H05K3/4061 ,  H05K3/4629 ,  H05K2201/0317 ,  H05K2201/0352 ,  H01L2924/00

Abstract: Disclosed herein is a multilayer low temperature co-fired ceramic (LTCC) structure comprising a multilayer low temperature co-fired ceramic comprising glass-ceramic dielectric layers with screen printed thick film inner conductors on portions of the layers and with thin film outer conductors deposited on the upper and lower outer surfaces of the LTCC. At least a portion of the thin film outer conductors is patterned in the form of lines and the spacings between the lines are less then 50 μm. Also disclosed is a process for making the LTCC structure.

Abstract translation: 本文公开了一种多层低温共烧陶瓷（LTCC）结构，其包括多层低温共烧陶瓷，​​其包含玻璃陶瓷电介质层，其中丝网印刷的厚膜内导体在层的部分上，并且薄膜外导体沉积在 LTCC的上下外表面。 薄膜外导体的至少一部分以线的形式图案化，并且线之间的间距小于50μm。 还公开了制造LTCC结构的方法。

公开(公告)号：US20140138132A1

公开(公告)日：2014-05-22

申请号：US14045377

申请日：2013-10-03

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： John Su Kyon

IPC: H05K3/44 ,  H05K1/02

CPC classification number: H05K3/4644 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/0209 ,  H05K3/108 ,  H05K2201/0352 ,  H05K2203/1476 ,  H05K2203/1572 ,  H01L2924/00

Abstract: Disclosed herein are a printed circuit board and a manufacturing method thereof. In the manufacturing method of the printed circuit board according to the exemplary embodiment of the present invention, primary copper plating layers are first formed on each of upper and lower surface portions of a core layer in a symmetrical structure, an insulating layer is formed on the primary copper plating layer of the upper surface side, and a secondary copper plating layer is continuously formed on the primary copper plating layer of only the lower surface side. Therefore plating thicknesses required for the front side and the rear side in an asymmetric structure may be uniform to have no plating deviation and non-peeling of an insulating layer (a dry film) for a circuit protection is prevented to have no short defect, thereby making it possible to form a fine circuit pattern.

Abstract translation: 这里公开了一种印刷电路板及其制造方法。 在根据本发明示例性实施例的印刷电路板的制造方法中，首先在对称结构的芯层的上表面部分和下表面部分中形成初级镀铜层，在 仅在下表面侧的初级镀铜层上连续形成上表面侧的初级镀铜层和二次镀铜层。 因此，不对称结构中的前侧和后侧所需的电镀厚度可以是均匀的，以防止电镀偏差，并且防止用于电路保护的绝缘层（干膜）的不剥离没有短的缺陷，由此 使得可以形成精细的电路图案。

公开(公告)号：US08729400B2

公开(公告)日：2014-05-20

申请号：US12272892

申请日：2008-11-18

Applicant: Yasushi Inagaki ,  Katsuyuki Sano

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H05K1/03

CPC classification number: H05K1/0237 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/66 ,  H01L24/81 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/0224 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/115 ,  H05K1/144 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09736 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An IC chip for a high frequency region, particularly a packaged substrate in which no malfunction or error occurs even if 3 GHz is exceeded. A conductive layer on a core substrate is formed at a thickness of 30 μm and a conductor circuit on an interlayer resin insulation layer is formed at a thickness of 15 μm. By thickening the conductive layer, the volume of the conductor can be increased and resistance can be reduced. Further, by using the conductive layer as a power source layer, the capacity of supply of power to an IC chip can be improved.

Abstract translation: 用于高频区域的IC芯片，特别是即使超过3GHz也不发生故障或错误的封装衬底。 在芯基板上形成厚度为30μm的导体层，形成层间树脂绝缘层上的导体电路，厚度为15μm。 通过增厚导电层，可以增加导体的体积并降低电阻。 此外，通过使用导电层作为电源层，可以提高向IC芯片供电的能力。