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    Conductive fabric with balanced mutual interference amongst conductors
    111.
    发明授权
    Conductive fabric with balanced mutual interference amongst conductors 失效
    导体之间具有平衡的相互干扰的导电织物

    公开(公告)号：US06951978B1

    公开(公告)日：2005-10-04

    申请号：US10739047

    申请日：2003-12-19

    Applicant: Richard S. Norman

    Inventor： Richard S. Norman

    IPC: H01B11/00 ,  H05K1/02

    CPC classification number: H05K1/0228 ,  H05K2201/09245 ,  H05K2201/09263

    Abstract: A conductive fabric including a plurality of conductive elements defining an alternating sequence of segments and cross-over regions. Within each of the segments, the conductive elements are arranged substantially in parallel; within each of the cross-over regions located between two adjacent segments, the conductive elements are permuted so as to allow the position occupied by at least one of the conductive elements to be different in each of the two adjacent segments. Between a pair of reference segments, each of the conductive elements experience coupling with respect to a subset of said conductive elements other than itself, the coupling experienced by each of the conductive elements being substantially identical.

    Abstract translation: 导电织物，其包括限定段和交叉区域的交替序列的多个导电元件。 在每个段内，导电元件基本上平行布置; 在位于两个相邻段之间的每个交叉区域内，导电元件被置换，以允许至少一个导电元件占据的位置在两个相邻段中的每一个中不同。 在一对参考段之间，每个导电元件相对于除本身之外的所述导电元件的子集经历耦合，由每个导电元件经历的耦合基本相同。

    Printed wiring board for controlling signal transmission using paired inductance and capacitance
    112.
    发明申请
    Printed wiring board for controlling signal transmission using paired inductance and capacitance 失效
    用于控制信号传输的印刷电路板，使用成对的电感和电容

    公开(公告)号：US20050168956A1

    公开(公告)日：2005-08-04

    申请号：US11094133

    申请日：2005-03-31

    Applicant: Toru Otaki ,  Tatsuo Nishino

    Inventor： Toru Otaki ,  Tatsuo Nishino

    IPC: H05K1/02 ,  H05K1/16 ,  H05K7/02

    CPC classification number: H05K1/0248 ,  H05K1/0242 ,  H05K1/025 ,  H05K1/165 ,  H05K2201/09263 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10689

    Abstract: In a printed wiring board in which wiring patterns for interconnecting a plurality of integrated circuits (ICs) operating with synchronizing signals, in order to make signal transmission times between a plurality of IC's the same, consecutively formed pairs of an inductance pattern and a capacitive pattern, are constructed at each of wiring patterns for interconnecting a plurality of IC's. By changing the shapes of the inductance pattern and the capacitive pattern, it is possible to adjust signal propagation velocities and signal transmission times.

    Abstract translation: 在用于使多个同步信号工作的集成电路（IC）互连的布线图案的印刷布线板中，为了使多个IC之间的信号传输时间相同，连续形成电感图案和电容图案对 被构造为用于互连多个IC的布线图案。 通过改变电感图形和电容图案的形状，可以调节信号传播速度和信号传输时间。

    Techniques for reducing the number of layers in a multilayer signal routing device
    114.
    发明申请
    Techniques for reducing the number of layers in a multilayer signal routing device 失效
    用于减少多层信号路由设备中的层数的技术

    公开(公告)号：US20040136168A1

    公开(公告)日：2004-07-15

    申请号：US10407460

    申请日：2003-04-07

    Inventor： Guy M.A.F. Duxbury ,  Aneta Wyrzykowska ,  Luigi G. Difilippo ,  Herman Kwong

    IPC: H02H003/00

    CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0005 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734 ,  Y10T29/49016 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: Techniques for reducing the number of layers in a multilayer signal routing device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method wherein the multilayer signal routing device has a plurality of electrically conductive signal path layers for routing a plurality of electrical signals thereon. The method may comprise forming a plurality of electrically conductive vias in the multilayer signal routing device for electrically connecting at least two of the plurality of electrically conductive signal path layers, wherein the plurality of vias are arranged so as to form at least one channel in at least one other of the plurality of electrically conductive signal path layers. The method may also comprise grouping at least a portion of the plurality of electrical signals based at least in part upon their proximity to the at least one channel so that they may be efficiently routed therein.

    Abstract translation: 公开了用于减少多层信号路由设备中的层数的技术。 在一个特定的示例性实施例中，这些技术可以被实现为一种方法，其中多层信号路由设备具有用于在其上路由多个电信号的多个导电信号路径层。 所述方法可以包括在所述多层信号路由设备中形成多个导电通孔，用于电连接所述多个导电信号路径层中的至少两个，其中所述多个通孔被布置成在其中形成至少一个通道 多个导电信号路径层中的至少另一个。 该方法还可以包括至少部分地基于它们与至少一个信道的接近度来分组多个电信号的至少一部分，使得它们可以被有效地路由到其中。

    Signal transmission circuit and electronic equipment
    116.
    发明申请
    Signal transmission circuit and electronic equipment 失效
    信号传输电路和电子设备

    公开(公告)号：US20040095200A1

    公开(公告)日：2004-05-20

    申请号：US10657178

    申请日：2003-09-09

    Inventor： Takanori Konishi

    IPC: H04B003/28

    CPC classification number: H05K1/0234 ,  H05K1/0231 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/097 ,  H05K2201/10022 ,  H05K2201/10166

    Abstract: The respective ends of input wiring on a printed wiring board of a signal transmission circuit are connected to an input terminal section and a transistor. The respective one terminals of a first capacitor and a first resistor are connected to the input wiring. A leading-side transmission path from a connection point with the first capacitor to a connection point with the input terminal section is formed by only a conductive pattern. An intermediate transmission path from the connection point with the first capacitor to a connection point with the first resistor includes two or more through holes or via holes. The intermediate transmission path is placed near grounding wiring on the printed wiring board. When one terminal of a second capacitor is connected to the intermediate transmission path, a transmission path between the respective connection points with the two capacitors includes one or more through holes or via holes.

    Abstract translation: 信号传输电路的印刷电路板上的输入布线的各个端部连接到输入端子部分和晶体管。 第一电容器和第一电阻器的相应的一个端子连接到输入布线。 从第一电容器的连接点到与输入端子部分的连接点的引导侧传输路径仅由导电图案形成。 从与第一电容器的连接点到与第一电阻器的连接点的中间传输路径包括两个或更多个通孔或通孔。 中间传输路径放置在印刷线路板上的接地布线附近。 当第二电容器的一个端子连接到中间传输路径时，具有两个电容器的各个连接点之间的传输路径包括一个或多个通孔或通孔。

    Split delay transmission line
    117.
    发明授权
    Split delay transmission line 有权
    分路延时传输线

    公开(公告)号：US06711640B1

    公开(公告)日：2004-03-23

    申请号：US09823147

    申请日：2001-03-29

    Applicant: Michael W. Leddige ,  James A. McCall

    Inventor： Michael W. Leddige ,  James A. McCall

    IPC: G06F1300

    CPC classification number: H05K1/0248 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/0979 ,  H05K2201/10159

    Abstract: A computer motherboard is described. That motherboard includes a memory controller and a memory section. A first trace couples the memory controller to the memory section, and a second trace couples the memory controller to the memory section. The first trace is joined with the second trace at the memory controller, the second trace is routed in parallel with the first trace, and the second trace is longer than the first trace. Also described is a computer system that includes this motherboard and a memory card.

    Abstract translation: 描述了计算机主板。 该主板包括一个内存控制器和一个内存部分。 第一迹线将存储器控制器耦合到存储器部分，并且第二迹线将存储器控制器耦合到存储器部分。 第一个跟踪与存储器控制器上的第二个跟踪相连，第二个跟踪与第一个跟踪并行，第二个跟踪长于第一个跟踪。 还描述了包括该主板和存储卡的计算机系统。

    Method and apparatus for reducing signal timing skew on a printed circuit board
    118.
    发明授权
    Method and apparatus for reducing signal timing skew on a printed circuit board 失效
    用于减少印刷电路板上的信号定时偏斜的方法和装置

    公开(公告)号：US06675313B2

    公开(公告)日：2004-01-06

    申请号：US10329494

    申请日：2002-12-27

    Applicant: David Cuthbert

    Inventor： David Cuthbert

    IPC: G06F104

    CPC classification number: H05K1/0248 ,  G06F1/10 ,  H05K1/0293 ,  H05K3/027 ,  H05K2201/09263 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/0979 ,  H05K2203/095 ,  H05K2203/107 ,  H05K2203/1115 ,  H05K2203/1338 ,  H05K2203/171 ,  H05K2203/175

    Abstract: An apparatus and method are described for reducing the timing skew on a printed circuit board including a plurality of conductive traces interconnecting a first node and a second node. At least one section is removed from at least one printed circuit board trace to thereby sever a trace and prevent signals passing from the first node to the second node from following the severed trace. In this manner, signal path length can be adjusted to reduce timing skews in the circuit. Sections are removed from the traces by using a laser, CVD, a router, a plasma or by passing sufficient current through weakened areas of the traces.

    Abstract translation: 描述了一种用于减少包括互连第一节点和第二节点的多个导电迹线的印刷电路板上的定时偏移的装置和方法。 至少一个部分从至少一个印刷电路板迹线移除，从而切断迹线并防止从第一节点传递到第二节点的信号不跟随切断的迹线。 以这种方式，可以调整信号路径长度以减少电路中的定时偏差。 通过使用激光，CVD，路由器，等离子体或者通过使足够的电流通过弱化区域从迹线中去除部分。

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