公开(公告)号：US20040196056A1

公开(公告)日：2004-10-07

申请号：US10805232

申请日：2004-03-22

Applicant: Broadcom Corporation

Inventor： James M. Kronrod

IPC: H01R004/66 ,  H01R013/648

CPC classification number: G01R1/203 ,  G01R19/16571 ,  H05K1/0268 ,  H05K2201/093 ,  H05K2201/09627

Abstract: System for measuring a thickness of a circuit component on a printed circuit board (PCB). The system includes a first circuit, a power plane, a power strip, a calibration strip, a temperature sensor, and a second circuit. The power plane is coupled to the first circuit. The power strip is for providing power to the power plane and is disposed in the PCB connected to the power plane. The power strip has at least two vias. The calibration strip has a predetermined width and is disposed in said PCB. The calibration strip has at least two vias for measuring a voltage drop. The temperature sensor is coupled to the calibration strip and configured to measuring a temperature of the calibration strip. The second circuit is coupled to the temperature sensor and configured to determine the thickness of the calibration strip based on at least the temperature of the calibration strip.

公开(公告)号：US06784526B1

公开(公告)日：2004-08-31

申请号：US09120117

申请日：1998-07-22

Applicant: Tsutomu Mezawa

Inventor： Tsutomu Mezawa

IPC: H01L2940

CPC classification number: H05K1/0233 ,  H01L2924/0002 ,  H05K1/0225 ,  H05K1/0248 ,  H05K1/0253 ,  H05K1/181 ,  H05K3/244 ,  H05K2201/086 ,  H05K2201/09254 ,  H05K2201/093 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/10689 ,  H05K2203/1572 ,  H01L2924/00

Abstract: According to the present invention, for a module in which a plurality of integrated circuit devices are mounted in parallel, the inductance generated by the unit length of a branched signal line on a motherboard is so set that it is smaller for a branched signal line a longer distance from its branching point to its distal end, and is so set that it is larger for a branched signal line having a shorter distance from its branching point to its distal end, so that the time required for transmission of a signal from the branching point to the distal end of each branched signal line is the same.

Abstract translation: 根据本发明，对于并联安装多个集成电路器件的模块，由母板上的分支信号线的单位长度产生的电感被设定为使分支信号线a 从其分支点到其远端的距离更长，并且被设定为对于从其分支点到其远端具有较短距离的分支信号线较大，使得从分支点传输信号所需的时间 指向每条分支信号线的末端是相同的。

公开(公告)号：US20040144562A1

公开(公告)日：2004-07-29

申请号：US10740459

申请日：2003-12-22

Applicant: Fujitsu Limited

Inventor： Kiyoshi Ishikawa

IPC: H05K007/06

CPC classification number: H05K1/025 ,  H05K1/0237 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/117 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/094 ,  H05K2201/0969 ,  H05K2201/09845

Abstract: To provide a printed wiring board where the impedance between pads through which differential signals pass has been set to a predetermined standard value. The printed wiring board includes a first conductor layer extending over an area excluding a hole formed for each pad group and filled with a dielectric, and a second conductor layer extending over an area containing areas facing the hole. The hole encompasses a plurality of areas facing predetermined respective pads which are adjacent to each other and which form the pad group from among the plurality of pads.

Abstract translation: 为了提供印刷电路板，其中差分信号通过的焊盘之间的阻抗已经被设置为预定的标准值。 印刷布线板包括在除了为每个焊盘组形成并填充有电介质的孔之外的区域上延伸的第一导体层，以及在包含面向孔的区域的区域上延伸的第二导体层。 该孔包围面对预定相应焊盘的多个区域，这些区域彼此相邻并且从多个焊盘中形成焊盘组。

公开(公告)号：US06767252B2

公开(公告)日：2004-07-27

申请号：US10267443

申请日：2002-10-09

Applicant: James L. McGrath ,  James P. Capadona ,  Daniel B. McGowan ,  Augusto P. Panella

Inventor： James L. McGrath ,  James P. Capadona ,  Daniel B. McGowan ,  Augusto P. Panella

IPC: H01R2370

CPC classification number: H05K1/117 ,  H01R12/721 ,  H01R13/6585 ,  H05K1/0219 ,  H05K2201/093 ,  H05K2201/0949 ,  H05K2201/0969 ,  H05K2201/09709 ,  H05K2201/09727

Abstract: A differential signal connector that is used for edge card application has a plurality of differential signal terminals and associated ground terminals arranged in “triplets”, i.e., distinct sets of three conductive terminals, each such triplet including a pair of differential signal terminals and one associated ground terminal. The ground terminal is flanked by the two differential signal terminals and each triplet is spaced apart from an adjacent triplet by a spacing which is greater than any single spacing between adjacent terminals within a triplet. Circuit boards to which such a connector is mounted are also disclosed and they have a particular pattern of termination traces, commonly taking the form of plated vias extending through the circuit board. These vias are arranged in a triangular pattern and the ground reference plane of the circuit board is provided with voids, one void being associated and encompassing a pair of the differential signal vias of a single terminal triplet. This reduces the capacitance of the signal vias and thereby increases the impedance of the circuit board within the launch area to lessen impedance discontinuities in the connector-circuit board interface.

Abstract translation: 用于边缘卡应用的差分信号连接器具有多个差分信号端子和以“三联体”排列的相关联的接地端子，即，三组导电端子的不同组合，每个这样的三联组件包括一对差分信号端子和一个相关联的 接地端。 接地端子侧面是两个差分信号端子，每个三极管与相邻的三通线隔开一个间隔，该间隔大于三线态内的相邻端子之间的任何单个间隔。 还公开了安装这种连接器的电路板，并且它们具有特定的端接迹线图案，通常采用延伸穿过电路板的电镀通孔的形式。 这些通孔被布置成三角形图案，并且电路板的接地参考平面设置有空隙，一个空隙相关联并且包围一对单个三端口的差分信号通路。 这减小了信号通路的电容，从而增加了发射区域内的电路板的阻抗，以减少连接器 - 电路板接口中的阻抗不连续性。

公开(公告)号：US20040106321A1

公开(公告)日：2004-06-03

申请号：US10719937

申请日：2003-11-21

Inventor： Andrew Harvey Barr ,  Jeremy Ian Wilson ,  Irving McKenzie Birmingham

IPC: H01R012/24

CPC classification number: H05K1/028 ,  H01B7/0009 ,  H01B7/0823 ,  H05K1/0224 ,  H05K2201/093 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/09745

Abstract: An embodiment of a cable system includes a cable that has a conductor, a power layer and dielectric material. The conductor is operative to carry a signal, the dielectric material is located at least partially between the conductor and the power layer, and the power layer is operative as ground. The power layer is formed of a conductive material and includes a first region and an adjacent second region. The first region includes a greater amount of the conductive material than the second region so that the power layer is less resistant to bending along the second region than along the first region. Methods and other systems are also provided.

公开(公告)号：US20040080378A1

公开(公告)日：2004-04-29

申请号：US10682994

申请日：2003-10-09

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Koji Furutani

IPC: H03H009/64

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L2924/0002 ,  H04B1/005 ,  H04B1/0057 ,  H04B1/006 ,  H04B1/52 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/0979 ,  H01L2924/00

Abstract: In a high-frequency module, intermediate ground electrodes are provided between a common ground electrode and upper-surface ground electrodes for mounting high-frequency components on an upper surface of a multilayer substrate. With regard to the number of via-hole conductors interconnecting ground electrodes, the number of via-hole conductors between the intermediate ground electrodes and the common ground electrode is larger than the number of via-hole conductors between the upper-surface ground electrodes and the intermediate ground electrodes.

Abstract translation: 在高频模块中，中间接地电极设置在公共接地电极和上表面接地电极之间，用于在多层基板的上表面上安装高频分量。 对于将接地电极互连的通孔导体的数量，中间接地电极和公共接地电极之间的通孔导体的数量大于上表面接地电极和通孔导体的数量 中间接地电极。

公开(公告)号：US06727780B2

公开(公告)日：2004-04-27

申请号：US10001781

申请日：2001-10-24

Applicant: Istvan Novak ,  Valerie St.Cyr ,  Michael C. Freda ,  Merle Tetreault

Inventor： Istvan Novak ,  Valerie St.Cyr ,  Michael C. Freda ,  Merle Tetreault

IPC: H03H738

CPC classification number: H05K1/0234 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K1/167 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10643 ,  Y02P70/611

Abstract: A method for achieving a desired value of electrical impedance between conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the conductors. The resistance elements may be annular resistors, and may provide the designer a greater degree of control of the system ESR. The annular resistors may comprise a first terminal, an annular resistor, and a second terminal. The second terminal may be located within the confines of the annular resistor. The annular resistors may be printed onto a conductive plane (e.g. a power plane or a ground plane), or may be a discrete component.

Abstract translation: 一种用于通过电耦合多个旁路电容器和在导体之间串联的对应的电阻元件来实现电力分配结构的导体之间的电阻抗的期望值的方法。 电阻元件可以是环形电阻器，并且可以向设计者提供对系统ESR的更大程度的控制。 环形电阻器可以包括第一端子，环形电阻器和第二端子。 第二端子可以位于环形电阻器的范围内。 环形电阻器可以印刷到导电平面（例如电源平面或接地平面）上，或者可以是分立的部件。

公开(公告)号：US20040061241A1

公开(公告)日：2004-04-01

申请号：US10261544

申请日：2002-09-30

Inventor： Edward P. Osburn ,  Erik W. Peter ,  Timothy M. Gates

IPC: H01L023/48 ,  H01L021/44

CPC classification number: H05K1/0262 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0231 ,  H05K1/0263 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/1003 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10704 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A method and an apparatus for improving the delivery and filtering of power to a semiconductor device is disclosed by organizing out interconnects (pins, balls, pads or other interconnects) used to carry power in a striped configuration that shortens the conductive path required between a power source and a semiconductor device and that reduces the resistance of that conductive path.

公开(公告)号：US20040058593A1

公开(公告)日：2004-03-25

申请号：US10670687

申请日：2003-09-25

Inventor： Shigeru Osada

IPC: H01R009/22

CPC classification number: H05K1/165 ,  H01F5/003 ,  H01F17/0033 ,  H05K3/222 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/097 ,  H05K2201/10636 ,  H05K2203/171 ,  Y02P70/611

Abstract: In a coupling adjusting structure for a double-tuned circuit according to the present invention, first and second coils are configured such that a pair of first conductive patterns formed on a first surface of a printed circuit and a corresponding pair of second conductive patterns formed on a second surface of the printed circuit board are connected via corresponding connecting conductors, thereby making the first and second coils low and thin. Also, one end of the first coil and the corresponding end of the second coil are disposed close to each other, a first ground conductive pattern is disposed at least on the first surface of the printed circuit, and a first jumper connected to the first ground conductive pattern is disposed between the first and second coils so as to adjust an inductive coupling of the double-tuned circuit, thereby achieving a coupling adjusting structure for a double-tuned circuit whose inductive coupling is adjustable.

Abstract translation: 在根据本发明的用于双调谐电路的耦合调整结构中，第一和第二线圈被配置成使得形成在印刷电路的第一表面上的一对第一导电图案和形成在 印刷电路板的第二表面通过相应的连接导体连接，从而使第一和第二线圈变薄和薄。 此外，第一线圈的一端和第二线圈的对应端部彼此靠近设置，第一接地导体图案至少设置在印刷电路的第一表面上，并且第一跳线连接到第一接地 导电图案设置在第一和第二线圈之间，以便调整双调谐电路的电感耦合，从而实现用于电感耦合可调节的双调谐电路的耦合调节结构。

公开(公告)号：US06710258B2

公开(公告)日：2004-03-23

申请号：US10125624

申请日：2002-04-18

Applicant: Stefano Oggioni ,  Roberto Ravanelli

Inventor： Stefano Oggioni ,  Roberto Ravanelli

IPC: H05K103

CPC classification number: H05K1/0222 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09618 ,  H05K2201/0969 ,  H05K2201/09809 ,  H05K2201/10734 ,  H01L2224/05599

Abstract: A multi-layered circuitized substrate for high-frequency applications. Conductive via-holes extend between two non-adjacent conductive layers for transmitting high-frequency signals therebetween. For each via-hole, shielding rings connectable to a reference voltage are provided, each ring formed in a corresponding intermediate conductive layer between the two non-adjacent conductive layers. The rings define a shielding coaxial structure for the via-hole. Preferably, the intermediate conductive layers are spaced apart from the via-hole, and particularly from respective lands at the ends thereof, in order to reduce stray capacitance associated with the via-hole without losing the shielding effect provided by the rings.

Abstract translation: 一种用于高频应用的多层电路衬底。 导电通孔在两个不相邻的导电层之间延伸，用于在它们之间传输高频信号。 对于每个通孔，提供可连接到参考电压的屏蔽环，每个环形成在两个不相邻的导电层之间的对应的中间导电层中。 这些环限定了用于通孔的屏蔽同轴结构。 优选地，中间导电层与通孔间隔开，特别是从其端部的相应焊盘间隔开，以便减少与通孔相关联的杂散电容，而不会损失由环提供的屏蔽效应。