公开(公告)号：US20050178669A1

公开(公告)日：2005-08-18

申请号：US11060019

申请日：2005-02-16

Applicant: John Strubbe

Inventor： John Strubbe

IPC: B05D5/12 ,  C23C18/16 ,  C23C18/18 ,  C23C18/31 ,  C23C22/66 ,  C23F1/20 ,  C23G1/12 ,  C25D5/44 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46

CPC classification number: C23C18/31 ,  C23C18/1653 ,  C23C18/1844 ,  C23C22/66 ,  C23F1/20 ,  C23G1/125 ,  C25D5/44 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4641 ,  H05K2201/0347 ,  H05K2201/09554

Abstract: This invention is a zincating process of aluminum surfaces for subsequent plating in which the aluminum surfaces are cleaned, contacted with an acidic etching solution comprising a peroxygen compound, the acidic etching solution being substantially free of corrosive nitrate compounds, and contacting the aluminum surfaces with a zincate solution containing 6-60 g/l zinc and 100-500 g/l hydroxide ion. The acidic etching solution is substantially free of toxic inorganic fluoride compounds in order to simplify waste treatment. This invention may be understood with reference to FIG. 2, in particular Step 6.

Abstract translation: 本发明是用于后续电镀的铝表面的锌化工艺，其中铝表面被清洁，与包含过氧化合物的酸性蚀刻溶液接触，酸性蚀刻溶液基本上不含腐蚀性硝酸盐化合物，并使铝表面与 含有6-60g / l锌和100-500g / l氢氧化物离子的锌酸盐溶液。 酸性蚀刻溶液基本上不含有毒的无机氟化物，以简化废物处理。 参照图1可以理解本发明。 2，特别是步骤6。

公开(公告)号：US20050124196A1

公开(公告)日：2005-06-09

申请号：US10987480

申请日：2004-11-11

Applicant: Kevin Olson ,  Alan Wang ,  Peter Elenius ,  Thomas Goodman

Inventor： Kevin Olson ,  Alan Wang ,  Peter Elenius ,  Thomas Goodman

IPC: H05K1/05 ,  H05K1/02 ,  H05K3/00 ,  H05K3/44 ,  H05K3/46 ,  H01R13/15

CPC classification number: H05K3/002 ,  H05K1/056 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/09645 ,  H05K2201/09827 ,  H05K2203/1105 ,  H05K2203/135

Abstract: A circuit board or each circuit board of a multi-layer circuit board includes an electrically conductive sheet coated with an insulating top layer covering one surface of the conductive sheet, an insulating bottom layer covering another surface of the conductive sheet and an insulating edge layer covering an edge of the conductive sheet. An insulating interlayer can be sandwiched between a pair of adjacent circuit boards of a multi-layer circuit board assembly. A landless through-hole or via can extend through one or more of the circuit boards for connecting electrical conductors on opposing surfaces thereof.

Abstract translation: 多层电路板的电路板或每个电路板包括涂覆有覆盖导电片的一个表面的绝缘顶层的导电片，覆盖导电片的另一表面的绝缘底层和覆盖 导电片的边缘。 绝缘中间层可以夹在多层电路板组件的一对相邻电路板之间。 无地通孔或通孔可以延伸通过一个或多个电路板，用于连接其相对表面上的电导体。

公开(公告)号：US06891732B2

公开(公告)日：2005-05-10

申请号：US10244210

申请日：2002-09-16

Applicant: Akihito Takano ,  Takahiro Iijima

Inventor： Akihito Takano ,  Takahiro Iijima

IPC: H05K1/05 ,  H01L23/10 ,  H01L23/12 ,  H01L23/36 ,  H05K1/02 ,  H05K1/18 ,  H05K3/44 ,  H05K3/46 ,  H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/0206 ,  H01L23/10 ,  H01L23/36 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K3/44 ,  H05K3/4608 ,  H05K2201/09554 ,  H05K2201/096

Abstract: A multilayer circuit board for mounting a semiconductor element thereon, comprising a core substrate of a metal material and a plurality of wiring layers stacked on either side of the core substrate, each of the stacked wiring layers being isolated from an adjacent wiring layer by an insulating layer interposed therebetween, the multilayer circuit board having an area at which a heat spreader for dissipating heat generated from the semiconductor element mounted on the circuit board is to be joined to the multilayer circuit board, wherein the multilayer circuit board allows the heat spreader to be joined to the core substrate without the insulating layers being interposed therebetween. A semiconductor device using the multilayer circuit board is also disclosed.

Abstract translation: 一种用于在其上安装半导体元件的多层电路板，包括金属材料的芯基板和堆叠在芯基板的两侧的多个布线层，每个堆叠的布线层通过绝缘体与相邻布线层隔离 层叠电路板，其中，多层电路板具有用于散热从安装在电路板上的半导体元件产生的散热器的散热器与多层电路板接合的区域，其中多层电路板允许散热器为 连接到芯基板上，绝缘层之间插入其中。 还公开了一种使用该多层电路板的半导体器件。

公开(公告)号：US20050092814A1

公开(公告)日：2005-05-05

申请号：US11000697

申请日：2004-12-01

Applicant: John Waldvogel ,  Brian Bielick ,  Herman Miller ,  Billy Van Cannon

Inventor： John Waldvogel ,  Brian Bielick ,  Herman Miller ,  Billy Van Cannon

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H05K3/38 ,  H05K3/40 ,  B23K31/02

CPC classification number: H05K1/021 ,  H05K1/182 ,  H05K3/0061 ,  H05K3/341 ,  H05K3/386 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/09554 ,  H05K2201/10166 ,  H05K2201/10969 ,  H05K2203/042 ,  H05K2203/063

Abstract: An electrical circuit apparatus (300) that includes: a substrate (330) having a ground layer (336), at least one device aperture (332), and at least one solder aperture (334); a heat sink (310); and an adhesive layer (320) for mechanically coupling the heat sink to the ground layer of the substrate such that at least a portion of the substrate device aperture overlaps the heat sink, the adhesive layer having at least one device aperture and at least one solder aperture, wherein aligning the at least one substrate solder aperture with the at least one adhesive layer solder aperture and aligning the at least one substrate device aperture with the at least one adhesive layer device aperture enables solder wetting in a predetermined area between the heat sink and the ground layer of the substrate.

Abstract translation: 一种电路设备（300），包括：具有接地层（336），至少一个器件孔（332）和至少一个焊料孔（334）的衬底（330）; 散热器（310）; 以及用于将所述散热器机械耦合到所述基板的接地层的粘合剂层（320），使得所述基板装置孔的至少一部分与所述散热器重叠，所述粘合剂层具有至少一个装置孔和至少一个焊料 孔，其中将所述至少一个衬底焊接孔与所述至少一个粘合剂层焊接孔对准并且将所述至少一个衬底器件孔与所述至少一个粘合剂层器件孔对准使得焊料在所述散热器和所述散热器之间的预定区域中润湿 衬底的接地层。

公开(公告)号：US06844504B2

公开(公告)日：2005-01-18

申请号：US10227768

申请日：2002-08-26

Applicant: Alan E. Wang ,  Kevin C. Olson ,  Thomas H. Di Stefano

Inventor： Alan E. Wang ,  Kevin C. Olson ,  Thomas H. Di Stefano

IPC: H05K1/05 ,  H05K3/00 ,  H05K3/06 ,  H05K3/44 ,  H05K3/46 ,  H05K1/03

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49167 ,  Y10T428/12361 ,  Y10T428/24322

Abstract: A circuit board layer 2 in accordance with the present invention includes a conductive sheet 4 sandwiched between an insulating top layer 10 and an insulating bottom layer 14. The top and bottom layers 10 and 14 and the conductive sheet 4 define the circuit board layer 2 having an edge that includes an edge 20 of the conductive sheet 4. An insulating edge layer 18 covers substantially all of the edge 20 of the conductive sheet 4.

Abstract translation: 根据本发明的电路板层2包括夹在绝缘顶层10和绝缘底层14之间的导电片4.顶层10和底层14以及导电片4限定电路板层2，其具有 包括导电片4的边缘20的边缘。绝缘边缘层18几乎覆盖导电片4的所有边缘20。

公开(公告)号：US06829823B2

公开(公告)日：2004-12-14

申请号：US10067551

申请日：2002-02-05

Applicant: Francis J. Downes, Jr. ,  Donald S. Farquhar ,  Elizabeth Foster ,  Robert M. Japp ,  Gerald W. Jones ,  John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

Inventor： Francis J. Downes, Jr. ,  Donald S. Farquhar ,  Elizabeth Foster ,  Robert M. Japp ,  Gerald W. Jones ,  John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

IPC: H01K310

CPC classification number: H05K3/4641 ,  H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.

Abstract translation: 一种制造多层互连结构的方法。 第一和第二导电构件分别形成在第一和第二电介质层上。 电介质层形成在导热层的相对表面上。 第一和第二导电层形成在第一介电层内。 第二导电层包括屏蔽信号导体并且位于第一导电层和导热层之间。 通过互连结构形成的电镀通孔（PTH）电连接到第一和第二导电构件中的一个和屏蔽信号导体之一。 形成在第一介电层上和第一导电构件的部分上的第三电介质层基本上覆盖在PTH上，并且包括用于提供从电子器件到屏蔽信号导体的电气路径的高密度互连层。

公开(公告)号：US20040231884A1

公开(公告)日：2004-11-25

申请号：US10849478

申请日：2004-05-19

Inventor： Kenneth Daryl Wong ,  Sean L. Bell

IPC: H05K007/20 ,  H05K001/11

CPC classification number: H05K3/44 ,  H05K3/0061 ,  H05K3/341 ,  H05K2201/09063 ,  H05K2201/09554 ,  H05K2201/10666 ,  H05K2203/1178 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed circuit board assembly employing a solder vent hole adjacent solder filled interconnect vias connecting to a conductive pallet, is disclosed. The solder vent hole allows gases to escape from an otherwise sealed cavity during solder reflow, relieving positive pressure and thereby allowing solder to flow into it. By providing an escape path for trapped air and gases generated during solder paste reflow, the out-gassing pressure and weight of the molten solder is sufficient to allow the solder paste to flow into the cavity.

Abstract translation: 公开了一种印刷电路板组件，其采用与连接到导电托盘的焊料填充的互连通孔相邻的焊剂通气孔。 焊锡通气孔允许气体在回流焊接过程中从另一个密封的空腔中逸出，减轻正压，从而允许焊料流入其中。 通过为焊膏回流期间产生的被捕获的空气和气体提供逃生路径，熔融焊料的排气压力和重量足以使焊膏流入空腔。

公开(公告)号：US20040187296A1

公开(公告)日：2004-09-30

申请号：US10735254

申请日：2003-12-12

Inventor： Kevin Cowles ,  A. David Erpelding

IPC: H01R043/00 ,  H05K003/36

CPC classification number: G11B5/486 ,  G11B5/02 ,  G11B5/11 ,  G11B5/112 ,  G11B5/3143 ,  G11B5/40 ,  G11B2005/0016 ,  H05K1/0215 ,  H05K3/4069 ,  H05K3/4084 ,  H05K3/44 ,  H05K2201/0305 ,  H05K2201/09554 ,  Y10T29/4903 ,  Y10T29/49032 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49165 ,  Y10T29/49179 ,  Y10T29/49224

Abstract: In an Integrated Lead Suspension system, it is desired that the stainless steel suspension is grounded to a controlled ground potential. This requires creating a grounding path between the stainless steel suspension and a copper trace layer through a layer of dielectric material that separates the stainless steel suspension and the copper layer. The copper trace layer and subsequently the stainless steel suspension can then be grounded to a controlled ground potential. This invention proposes several methods of creating a ground path between the stainless steel suspension and the copper trace layer.

Abstract translation: 在集成式悬挂系统中，希望不锈钢悬架接地到受控的接地电位。 这需要通过分离不锈钢悬浮液和铜层的介电材料层在不锈钢悬浮液和铜迹线层之间形成接地路径。 铜迹线层和随后的不锈钢悬浮液然后可以接地到受控的接地电位。 本发明提出了在不锈钢悬浮液和铜迹线层之间产生接地路径的几种方法。

公开(公告)号：US06750405B1

公开(公告)日：2004-06-15

申请号：US09690485

申请日：2000-10-17

Applicant: Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

Inventor： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

IPC: H01R1204

CPC classification number: H05K3/445 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/056 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/0052 ,  H05K3/0094 ,  H05K3/06 ,  H05K3/108 ,  H05K3/426 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0919 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/10734 ,  H05K2203/0323 ,  H05K2203/0574 ,  H05K2203/0733 ,  H05K2203/1394 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers. Thereafter, the surfaces of the photoimageable material, vias and through holes are metalized by copper plating. This is preferably done by protecting the remainder of the circuitry with photoresist and utilizing photolithographic techniques. The photoresist is thereafter removed, leaving a circuit board or card having metalization on both sides, vias extending from both sides to the copper layer in the center, plated through holes connecting the two outer circuitized copper layers.

Abstract translation: 形成印刷电路板或电路卡的方法设置有用作夹在一对可光成像的电介质层之间的电力平面的金属层。 光刻图形金属填充的通孔和光成像的电镀通孔位于光图案化材料中，信号电路位于每个介电材料的表面上，并连接到通孔和电镀通孔。 边界可以在板或卡周围，包括从电介质层之一的边缘终止的金属层。 铜箔上设有间隙孔。 可光成像的可固化介电材料的第一和第二层设置在作为可光成像的材料的铜的相对侧上。 图案在可光成象材料的第一层和第二层上显影，以通过通孔显露金属层。 在铜中的间隙孔处，通孔被开发成在两个电介质层中图案化孔。 此后，可光成像材料，通孔和通孔的表面通过镀铜进行金属化。 这优选通过用光致抗蚀剂和利用光刻技术保护电路的其余部分来实现。 然后去除光致抗蚀剂，留下在两侧具有金属化的电路板或卡，其中心的两侧延伸到铜层，通孔连接两个外部电路化的铜层。

公开(公告)号：US20040065960A1

公开(公告)日：2004-04-08

申请号：US10263909

申请日：2002-10-03

Applicant: International Business Machines Corporation

Inventor： Frank D. Egitto ,  Elizabeth Foster ,  Raymond T. Galasco ,  Voya R. Markovich ,  Manh-Quan Tam Nguyen

IPC: H01L023/48

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2203/0733 ,  H01L2924/00

Abstract: The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.

Abstract translation: 通过在层叠到用作接地平面或电源平面的导电金属芯的第一电介质层中提供盲目的无地通孔来改善电子封装的密度和利用堆叠盲孔的子组件的电可靠性。 通过延伸到芯的电介质层提供孔。 使用金属芯作为阴极电解沉积诸如铜的金属，或者无电渗入孔中。 金属沉积在芯上并逐渐建立在孔中以达到通孔所需的深度。 第二电介质层被层压到第一电介质层，并且具有与第一通孔对准的第二层盲孔。 该第二通孔可以由常规电镀技术形成。 可以以这种方式组装具有堆叠的盲孔的多个电介质层。