公开(公告)号：US09609751B2

公开(公告)日：2017-03-28

申请号：US14251486

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Houssam Wafic Jomaa ,  Omar James Bchir ,  Chin-Kwan Kim

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H01L23/498

CPC classification number: H05K1/112 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K3/422 ,  H05K3/425 ,  H05K3/429 ,  H05K2201/0344 ,  H05K2201/09036 ,  H05K2201/10378

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.

公开(公告)号：US09288901B2

公开(公告)日：2016-03-15

申请号：US14264499

申请日：2014-04-29

Applicant: Roger G. Markham ,  Ronald Steven Cok ,  Yongcai Wang ,  Mitchell Lawrence Wright

Inventor： Roger G. Markham ,  Ronald Steven Cok ,  Yongcai Wang ,  Mitchell Lawrence Wright

IPC: H01L33/42 ,  H05K1/02 ,  H01B1/02 ,  H05K3/10 ,  H05K3/18

CPC classification number: H05K1/0298 ,  H01B1/02 ,  H05K1/0293 ,  H05K1/097 ,  H05K1/165 ,  H05K3/103 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/181 ,  H05K3/246 ,  H05K3/247 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/035 ,  H05K2201/09036 ,  H05K2201/10098 ,  H05K2203/1476 ,  H05K2203/173

Abstract: A thin-film multi-layer micro-wire structure includes a substrate and a layer located on the substrate or forming a part of the substrate. One or more micro-channels are located in the layer. Each micro-channel has a width less than or equal to 20 microns. A cured electrically conductive micro-wire is located only within each micro-channel. The micro-wire has a thickness less than or equal to 20 microns, including silver nano-particles, and having a percent ratio of silver that is greater than or equal to 40% by weight. An electrolessly plated layer is located at least partially within each micro-channel between the micro-wire and the layer surface and in electrical contact with the micro-wire. The plated layer has a thickness less than a thickness of the micro-wire so that the micro-wire and plated layer form the thin-film multi-layer micro-wire.

Abstract translation: 薄膜多层微线结构包括衬底和位于衬底上或形成衬底的一部分的层。 一个或多个微通道位于该层中。 每个微通道具有小于或等于20微米的宽度。 固化的导电微线仅位于每个微通道内。 微线具有小于或等于20微米的厚度，包括银纳米颗粒，并且银的百分比大于或等于40重量％。 无电镀层至少部分地位于微线和层表面之间的每个微通道内并与微线电接触。 电镀层的厚度小于微线的厚度，使得微线和镀层形成薄膜多层微线。

公开(公告)号：US09184135B1

公开(公告)日：2015-11-10

申请号：US14569010

申请日：2014-12-12

Applicant: Triton Microtechnologies

Inventor： Tim Mobley ,  Roupen Leon Keusseyan ,  Charles Tucker

IPC: H01L23/538 ,  H05K3/00 ,  H05K1/03 ,  H05K1/09 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13138 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/007 ,  H05K2201/0344 ,  H05K2201/09481 ,  H05K2201/09563 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/11009 ,  H01L2924/014 ,  H01L2924/01014 ,  H01L2224/45099

Abstract: A system for backside metallization and reinforcement of glass substrates to provide support and protection during handling and processing of the glass substrates. A sacrificial substrate is removeably attached to a glass substrate comprising through-holes, backside metallized pads, and under-bump metallization (UBM) pads enclosing the backside metallized pads. The sacrificial substrate comprises a sacrificial layer, an opaque film, and an adhesive. The sacrificial substrate protects the backside metallized pads and UBM pads, and reinforces the glass substrate.

Abstract translation: 用于玻璃基板的背面金属化和增强的系统，以在玻璃基板的处理和加工期间提供支撑和保护。 牺牲衬底可移除地附接到包括通孔，背面金属化焊盘和包围背面金属化焊盘的凸起下金属化（UBM）焊盘的玻璃衬底。 牺牲衬底包括牺牲层，不透明膜和粘合剂。 牺牲基板保护背面金属化焊盘和UBM焊盘，并加强玻璃基板。

公开(公告)号：US20150313009A1

公开(公告)日：2015-10-29

申请号：US14264499

申请日：2014-04-29

Applicant: ROGER G. MARKHAM ,  Ronald Steven Cok ,  Yongcai Wang ,  Mitchell Lawrence Wright

Inventor： ROGER G. MARKHAM ,  Ronald Steven Cok ,  Yongcai Wang ,  Mitchell Lawrence Wright

IPC: H05K1/02 ,  H05K3/10 ,  H05K3/18 ,  H01B1/02

CPC classification number: H05K1/0298 ,  H01B1/02 ,  H05K1/0293 ,  H05K1/097 ,  H05K1/165 ,  H05K3/103 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/181 ,  H05K3/246 ,  H05K3/247 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/035 ,  H05K2201/09036 ,  H05K2201/10098 ,  H05K2203/1476 ,  H05K2203/173

Abstract: A thin-film multi-layer micro-wire structure includes a substrate and a layer located on the substrate or forming a part of the substrate. One or more micro-channels are located in the layer. Each micro-channel has a width less than or equal to 20 microns. A cured electrically conductive micro-wire is located only within each micro-channel. The micro-wire has a thickness less than or equal to 20 microns, including silver nano-particles, and having a percent ratio of silver that is greater than or equal to 40% by weight. An electrolessly plated layer is located at least partially within each micro-channel between the micro-wire and the layer surface and in electrical contact with the micro-wire. The plated layer has a thickness less than a thickness of the micro-wire so that the micro-wire and plated layer form the thin-film multi-layer micro-wire.

Abstract translation: 薄膜多层微线结构包括衬底和位于衬底上或形成衬底的一部分的层。 一个或多个微通道位于该层中。 每个微通道具有小于或等于20微米的宽度。 固化的导电微线仅位于每个微通道内。 微线具有小于或等于20微米的厚度，包括银纳米颗粒，并且银的百分比大于或等于40重量％。 无电镀层至少部分地位于微线和层表面之间的每个微通道内并与微线电接触。 电镀层的厚度小于微线的厚度，使得微线和镀层形成薄膜多层微线。

公开(公告)号：US09142501B2

公开(公告)日：2015-09-22

申请号：US14447908

申请日：2014-07-31

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Minhua Lu ,  Eric D. Perfecto ,  David J. Russell ,  Wolfgang Sauter ,  Krystyna Semkow ,  Thomas A. Wassick

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  H01L21/768 ,  H05K1/09 ,  H05K3/40 ,  H05K3/34

CPC classification number: H01L23/49816 ,  H01L21/76843 ,  H01L21/76885 ,  H01L23/49866 ,  H01L2224/11 ,  H05K1/09 ,  H05K3/3478 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0344 ,  H05K2201/09745 ,  H05K2203/041

Abstract: An interconnect structure that includes a substrate having an electrical component present therein, and a under-bump metallurgy (UBM) stack that is present in contact with a contact pad to the electrical component that is present in the substrate. The UBM stack includes a metallic adhesion layer that is direct contact with the contact pad to the electrical component, a copper (Cu) seed layer that is in direct contact with the metallic adhesion layer layer, a first nickel (Ni) barrier layer that is present in direct contact with copper (Cu) seed layer, and a layered structure of at least one copper (Cu) conductor layer and at least one second nickel (Ni) barrier layer present on the first nickel (Ni) barrier layer. A solder ball may be present on second nickel (Ni) barrier layer.

Abstract translation: 一种互连结构，其包括其中存在电气部件的基板以及与接触焊盘接触的凸起下冶金（UBM）堆叠，所述凸块冶金（UBM）堆叠存在于所述基板中的所述电气部件。 UBM堆叠包括与接触焊盘直接接触电气部件的金属粘合层，与金属粘附层层直接接触的铜（Cu）种子层，第一镍（Ni）阻挡层， 存在于铜（Cu）种子层的直接接触中，以及存在于第一镍（Ni）阻挡层上的至少一个铜（Cu）导体层和至少一个第二镍（Ni）阻挡层的层状结构。 第二镍（Ni）阻挡层上可能存在焊球。

公开(公告)号：US20150075851A1

公开(公告)日：2015-03-19

申请号：US14548725

申请日：2014-11-20

Applicant: IBIDEN CO., LTD.

Inventor： Masahiro KANEKO ,  Satoru KOSE ,  Hirokazu HIGASHI

IPC: H05K3/42 ,  H05K1/03 ,  H05K3/22 ,  H05K1/11

CPC classification number: H05K3/42 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85001 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0313 ,  H05K1/113 ,  H05K1/115 ,  H05K3/007 ,  H05K3/108 ,  H05K3/22 ,  H05K3/388 ,  H05K2201/0344 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/1377 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed wiring board includes an interlayer resin insulation layer having a penetrating hole, a conductive circuit formed on a first surface of the interlayer resin insulation layer, a filled via conductor formed in the penetrating hole of the interlayer resin insulation layer and connected to the conductive circuit, a first surface-treatment coating structure formed on a first surface of the filled via conductor and having an electroless plating structure, and a second surface-treatment coating structure formed on a second surface of the filled via conductor on an opposite side with respect to the first surface-treatment coating structure and having an electroless plating structure. The filled via conductor includes a first conductive layer formed on side wall of the penetrating hole and a plated material filling the penetrating hole, and the first surface-treatment coating structure has a thickness which is different from a thickness of the second surface-treatment coating structure.

Abstract translation: 印刷电路板包括具有贯通孔的层间树脂绝缘层，形成在层间树脂绝缘层的第一表面上的导电电路，形成在层间树脂绝缘层的穿透孔中并与导电 电路，形成在填充的通路导体的第一表面上并具有无电解电镀结构的第一表面处理涂层结构和形成在填充通孔导体的第二表面上的第二表面处理涂层结构，该第二表面处理涂层结构相对于 涉及第一表面处理涂层结构并具有化学镀层结构。 填充的通孔导体包括形成在穿透孔的侧壁上的第一导电层和填充穿透孔的电镀材料，第一表面处理涂层结构的厚度与第二表面处理涂层的厚度不同 结构体。

公开(公告)号：US08410376B2

公开(公告)日：2013-04-02

申请号：US12840696

申请日：2010-07-21

Applicant: Masahiro Kaneko ,  Satoru Kose ,  Hirokazu Higashi

Inventor： Masahiro Kaneko ,  Satoru Kose ,  Hirokazu Higashi

IPC: H05K1/11

CPC classification number: H05K3/42 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85001 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0313 ,  H05K1/113 ,  H05K1/115 ,  H05K3/007 ,  H05K3/108 ,  H05K3/22 ,  H05K3/388 ,  H05K2201/0344 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/1377 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed wiring board includes an interlayer resin insulation layer having a penetrating hole for a via conductor, a conductive circuit formed on one surface of the interlayer resin insulation layer, a via conductor formed in the penetrating hole and having a protruding portion protruding from the other surface of the interlayer resin insulation layer, and a surface-treatment coating formed on the surface of the protruding portion of the via conductor. The via conductor is connected to the conductive circuit and has a first conductive layer formed on the side wall of the penetrating hole and a plated layer filling the penetrating hole.

Abstract translation: 印刷电路板包括：具有用于通路导体的贯通孔的层间树脂绝缘层，形成在层间树脂绝缘层的一个表面上的导电电路;形成在该贯通孔中的通孔导体，并且具有从另一个突出的突出部 层间树脂绝缘层的表面和形成在通孔导体的突出部分的表面上的表面处理涂层。 通孔导体连接到导电电路，并且具有形成在穿透孔的侧壁上的第一导电层和填充穿透孔的镀层。

公开(公告)号：US20120055702A1

公开(公告)日：2012-03-08

申请号：US13320285

申请日：2010-05-27

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H05K1/02 ,  H05K3/10

CPC classification number: H05K1/181 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K1/0221 ,  H05K1/0256 ,  H05K1/0274 ,  H05K1/0284 ,  H05K1/118 ,  H05K1/16 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/207 ,  H05K3/246 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4664 ,  H05K3/4694 ,  H05K2201/0344 ,  H05K2201/0367 ,  H05K2201/09109 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T29/49155

Abstract: A compliant printed flexible circuit including a flexible polymeric film and at least one dielectric layer bonded to the polymeric film with recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the recesses to form a circuit geometry. At least one dielectric covering layer is printed over at least the circuit geometry. Openings can be printed in the dielectric covering layer to provide access to at least a portion of the circuit geometry.

Abstract translation: 包括柔性聚合物膜和柔性聚合物膜的柔性印刷柔性电路以及与聚合物膜结合的至少一个介电层，其具有对应于目标电路几何形状的凹部。 在至少一部分凹部中印刷导电材料以形成电路几何形状。 至少一个电介质覆盖层至少印刷在电路几何形状上。 开口可以印刷在电介质覆盖层中以提供对电路几何形状的至少一部分的访问。

公开(公告)号：US20120037405A1

公开(公告)日：2012-02-16

申请号：US13265042

申请日：2010-05-24

Applicant: Akihisa Hamazawa ,  Koji Nishimura ,  Hideki Goda

Inventor： Akihisa Hamazawa ,  Koji Nishimura ,  Hideki Goda

IPC: H05K1/03 ,  H05K3/00

CPC classification number: H05K1/0277 ,  H05K1/0346 ,  H05K1/0373 ,  H05K1/0393 ,  H05K3/108 ,  H05K2201/0154 ,  H05K2201/0209 ,  H05K2201/0344 ,  H05K2201/068 ,  Y10T29/49124

Abstract: An object of the present invention is to provide a flexible circuit board that maintains high insulation reliability, exhibits high wiring adhesion, has low thermal expansion, and allows the formation of a fine circuit thereon. Specifically, the present invention provides a flexible circuit board, wherein at least a nickel plating layer is laminated on a polyimide film to form a polyimide film provided with a nickel plating layer and a wiring pattern is applied to the nickel plating layer thereof. The polyimide film has a thermal expansion coefficient of 0 to 8 ppm/° C. in the temperature range from 100 to 200° C., and the nickel plating layer has a thickness of 0.03 to 0.3 μm.

Abstract translation: 本发明的目的是提供一种保持高绝缘可靠性，显示出高布线附着力，低热膨胀性并且允许在其上形成微细电路的柔性电路板。 具体地说，本发明提供一种挠性电路基板，其中，在聚酰亚胺膜上层叠有至少一层镍镀层，形成具有镀镍层的聚酰亚胺膜，并且对其镀镍层施加布线图案。 在100〜200℃的温度范围内，聚酰亚胺膜的热膨胀系数为0〜8ppm /℃，镀镍层的厚度为0.03〜0.3μm。

公开(公告)号：US20100059386A1

公开(公告)日：2010-03-11

申请号：US12513611

申请日：2006-11-06

Applicant: Hisamitsu Yamamoto

Inventor： Hisamitsu Yamamoto

IPC: C23C28/02 ,  C25D3/38 ,  C25D5/00 ,  C25D5/56

CPC classification number: C23C18/44 ,  C23C18/1653 ,  C23C18/2086 ,  C23C18/30 ,  C25D5/02 ,  C25D5/56 ,  H05K1/0346 ,  H05K3/181 ,  H05K3/422 ,  H05K3/427 ,  H05K2201/0344 ,  H05K2203/124

Abstract: A surface of an object to be plated is subjected to a treatment for palladium catalyst impartation to impart a palladium catalyst to the surface of an insulating part thereof. A palladium conductor layer is formed on the insulating part from a solution for palladium conductor layer formation which contains a palladium compound, an amine compound, and a reducing agent. On the palladium conductor layer is then directly formed a copper deposit by electroplating. Thus, the work is converted to a conductor with the solution for palladium conductor layer formation, which is neutral, without using an electroless copper plating solution which is highly alkaline. Consequently, the polyimide is prevented from being attacked and no adverse influence is exerted on adhesion. By adding an azole compound to the solution for palladium conductor layer formation, a palladium conductor layer is prevented from depositing on copper. Thus, the reliability of connection between the copper part present on a substrate and the copper deposit formed by electroplating is significantly high.

Abstract translation: 对被镀物体的表面进行钯催化剂的处理，将钯催化剂赋予其绝缘部分的表面。 在包含钯化合物，胺化合物和还原剂的钯导体层形成用溶液的绝缘部上形成钯导体层。 然后在钯导体层上通过电镀直接形成铜沉积物。 因此，不用使用高碱性化学镀铜溶液，将工件转化为具有中性的钯导体层形成溶液的导体。 因此，防止聚酰亚胺受到攻击，并且不会对粘合产生不利影响。 通过向溶液中添加唑化合物以形成钯导体层，可以防止钯导体层沉积在铜上。 因此，存在于基板上的铜部分与通过电镀形成的铜沉积物之间的连接的可靠性显着地高。