公开(公告)号：US06706973B2

公开(公告)日：2004-03-16

申请号：US10200941

申请日：2002-07-23

Applicant: Thomas H. DiStefano ,  Joseph Fjelstad

Inventor： Thomas H. DiStefano ,  Joseph Fjelstad

IPC: H05K116

CPC classification number: H05K3/462 ,  H01L23/49827 ,  H01L23/5385 ,  H01L2924/0002 ,  H01R12/523 ,  H01R12/714 ,  H01R13/2414 ,  H01R43/0256 ,  H05K1/0272 ,  H05K1/036 ,  H05K1/056 ,  H05K1/116 ,  H05K3/0032 ,  H05K3/326 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/0382 ,  H05K2201/0397 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2203/0554 ,  H05K2203/0582 ,  H05K2203/135 ,  H05K2203/308 ,  Y10T29/49126 ,  Y10T29/49133 ,  Y10T29/49137 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1744 ,  H01L2924/00

Abstract: An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact extends from a central conductor, and has a peripheral portion adapted to contract radially inwardly toward the central conductor response to a force applied by a contact pad defining a central hole on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts contract radially inwardly and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by friction welding, or by a conductive bonding material carried on the contacts themselves.

公开(公告)号：US06700072B2

公开(公告)日：2004-03-02

申请号：US09779117

申请日：2001-02-08

Applicant: Thomas H. Distefano ,  Joseph Fjelstad

Inventor： Thomas H. Distefano ,  Joseph Fjelstad

IPC: H05K103

CPC classification number: H05K3/462 ,  H01L23/49827 ,  H01L23/5385 ,  H01L2924/0002 ,  H01R12/523 ,  H01R12/714 ,  H01R13/2414 ,  H01R43/0256 ,  H05K1/0272 ,  H05K1/036 ,  H05K1/056 ,  H05K1/116 ,  H05K3/0032 ,  H05K3/326 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/0382 ,  H05K2201/0397 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2203/0554 ,  H05K2203/0582 ,  H05K2203/135 ,  H05K2203/308 ,  Y10T29/49126 ,  Y10T29/49133 ,  Y10T29/49137 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1744 ,  H01L2924/00

Abstract: An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact extends from a central conductor, and has a peripheral portion adapted to contract radially inwardly toward the central conductor response to a force applied by a contact pad defining a central hole on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts contract radially inwardly and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by friction welding, or by a conductive bonding material carried on the contacts themselves.

Abstract translation: 用于微电子电路板之间的互连的插入件在其表面具有接触。 每个接触件从中心导体延伸，并且具有适于从中心导体径向向内收缩的外围部分，以响应由在所接合的电路板上限定中心孔的接触垫施加的力。 因此，当电路板被内插件压缩时，触头径向向内收缩并且擦拭穿过焊盘。 擦拭动作有助于通过摩擦焊接将接触件接合到焊盘，或者通过接触件本身承载的导电接合材料。

公开(公告)号：US20040001325A1

公开(公告)日：2004-01-01

申请号：US10227768

申请日：2002-08-26

Inventor： Alan E. Wang ,  Kevin C. Olson ,  Thomas H. Di Stefano

IPC: H05K001/18

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49167 ,  Y10T428/12361 ,  Y10T428/24322

Abstract: A circuit board layer 2 in accordance with the present invention includes a conductive sheet 4 sandwiched between an insulating top layer 10 and an insulating bottom layer 14. The top and bottom layers 10 and 14 and the conductive sheet 4 define the circuit board layer 2 having an edge that includes an edge 20 of the conductive sheet 4. An insulating edge layer 18 covers substantially all of the edge 20 of the conductive sheet 4.

Abstract translation: 根据本发明的电路板层2包括夹在绝缘顶层10和绝缘底层14之间的导电片4.顶层10和底层14以及导电片4限定电路板层2，其具有 包括导电片4的边缘20的边缘。绝缘边缘层18几乎覆盖导电片4的所有边缘20。

公开(公告)号：US20030188429A1

公开(公告)日：2003-10-09

申请号：US10435279

申请日：2003-05-08

Applicant: International Business Machines Corporation

Inventor： Takayuki Haze ,  Tsuneo Yabuuchi

IPC: H01K003/22 ,  H05K003/02

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0035 ,  H05K3/385 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/086 ,  H05K2203/087 ,  H05K2203/1157 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49165

Abstract: The method for producing a printed wiring board comprising the steps of preparing a conductive substrate, forming an insulating layer on one surface of the said substrate, forming at least one via hole in the insulating layer, thermally curing the insulating layer, and reducing at least one oxidized layer formed on the other conductive surface of the substrate during the curing operation. Alternatively, the thermal cure may be accomplished in an atmosphere (e.g., reducing gas, inactive gas, or mixtures thereof) not conducive to oxide formation on metallized circuit surfaces.

Abstract translation: 一种制造印刷电路板的方法，包括以下步骤：制备导电基板，在所述基板的一个表面上形成绝缘层，在绝缘层中形成至少一个通孔，热固化绝缘层，并至少减少 在固化操作期间在基板的另一导电表面上形成一个氧化层。 或者，热固化可以在不利于金属化电路表面上的氧化物形成的气氛（例如还原气体，惰性气体或其混合物）中完成。

公开(公告)号：US20030147227A1

公开(公告)日：2003-08-07

申请号：US10263849

申请日：2002-10-03

Applicant: International Business Machines Corporation

Inventor： Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

IPC: H05K001/11 ,  H05K001/14

CPC classification number: H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4641 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1092

Abstract: A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.

Abstract translation: 多层互连结构和形成方法。 在第一实施例中，第一和第二液晶聚合物（LCP）电介质层分别直接接合到导热层的第一和第二相对表面，没有外在粘合材料将导热层与第一或第二液晶聚合物 LCP电介质层。 在第二实施例中，第一和第二2S1P子结构分别直接接合到LCP电介质接合层的第一和第二相对表面，没有外部粘合材料将LCP电介质接合层与第一或第二2S1P子结构结合。

公开(公告)号：US06576148B1

公开(公告)日：2003-06-10

申请号：US09259890

申请日：1999-02-22

Applicant: Victor Wing-Chun Shum ,  Randall George Simmons

Inventor： Victor Wing-Chun Shum ,  Randall George Simmons

IPC: B44C122

CPC classification number: H05K3/4084 ,  G11B5/112 ,  G11B5/40 ,  G11B5/4833 ,  G11B5/484 ,  H05K1/0259 ,  H05K1/056 ,  H05K2201/0394 ,  H05K2201/09554

Abstract: An integrated lead suspension is formed from a laminate of three materials in a variety of configurations having from three to five layers. The materials are stainless steel, polyimide and copper. Each layer is essentially homogeneous, but may be formed with one or more holes or voids prior to the formation of the laminate. The voids allow dielectric material to be removed from the area beneath the conductors to simplify processing and reduce the cost of the suspensions. The voids can also form a window through which conductors can be shorted to other conductive layers to form an electrostatic discharge shunt. Alternatively, the shorting of conductors can be used as a cross-over for various conductors.

Abstract translation: 集成的铅悬浮体由具有三至五层的各种构造的三种材料的层压体形成。 材质为不锈钢，聚酰亚胺和铜。 每个层基本上是均匀的，但是在形成层压体之前可以形成有一个或多个孔或空隙。 空隙允许介电材料从导体下面的区域移除，以简化处理并降低悬架的成本。 空隙也可以形成窗口，通过该窗口，导体可以与其它导电层短路以形成静电放电分路。 或者，导体的短路可以用作各种导体的交叉。

公开(公告)号：US06555763B1

公开(公告)日：2003-04-29

申请号：US09397016

申请日：1999-09-15

Applicant: Koki Hirasawa ,  Teruo Ono

Inventor： Koki Hirasawa ,  Teruo Ono

IPC: H01R1204

CPC classification number: H05K3/4629 ,  H01L21/4857 ,  H01L23/49805 ,  H01L23/5383 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0306 ,  H05K1/056 ,  H05K3/423 ,  H05K3/44 ,  H05K3/4617 ,  H05K3/4652 ,  H05K2201/09554 ,  H05K2201/09563 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A multilayered circuit board for a semiconductor chip module includes an underlying board, insulating layers, fixed-potential wiring layers, via holes, and metal layers. The underlying board has a major surface made of a metal material to which a fixed potential is applied. The insulating layers are stacked on the major surface of the underlying board and have wiring layers formed on their surfaces. The fixed-potential wiring layers constitute part of the wiring layers formed on the insulating layers. The via holes are formed below the fixed-potential wiring layers to extend through the insulating layers. The metal layers are filled in the via holes so as to make upper ends be connected to the lower surfaces of the fixed-potential wiring layers. One of the insulating layers in contact with the major surface of the underlying board is formed on the underlying board while the lower end of the metal layer is in contact with the major surface of the underlying board. The other insulating layer formed on the insulating layer in contact with the major surface of the underlying board is stacked while the lower end of the metal layer is in contact with the upper surface of the fixed-potential wiring layer of one insulating layer.

Abstract translation: 用于半导体芯片模块的多层电路板包括下面的板，绝缘层，固定电位布线层，通孔和金属层。 底板具有由施加固定电位的金属材料制成的主表面。 绝缘层层叠在下层基板的主表面上，并且在其表面上形成布线层。 固定电位布线层构成在绝缘层上形成的布线层的一部分。 通孔形成在固定电位布线层的下方，延伸穿过绝缘层。 金属层填充在通孔中，以使上端连接到固定电位布线层的下表面。 与下面的板的主表面接触的绝缘层之一形成在下面的板上，而金属层的下端与下面的板的主表面接触。 叠层在绝缘层上形成的与基板的主表面接触的绝缘层，同时金属层的下端与一个绝缘层的固定电位布线层的上表面相接触。

公开(公告)号：US20030025192A1

公开(公告)日：2003-02-06

申请号：US10254926

申请日：2002-09-25

Applicant: Tessera, Inc.

Inventor： Belgacem Haba

IPC: H01L023/48

CPC classification number: H01L24/50 ,  H01L21/4857 ,  H01L23/142 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/386 ,  H05K3/423 ,  H05K3/445 ,  H05K2201/0382 ,  H05K2201/09554 ,  H05K2203/0582 ,  H05K2203/135 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electrically conductive article such as a sheet having holes therein is coated with a dielectric polymer using a multi-stage electrophoretic deposition process. A coating of uncured polymer is deposited electrophoretically and then cured. After the first polymer is cured, the part is subject to a further electrophoretic deposition process and further curing. Use of a second electrophoretic deposition step allows effective coating of parts having small holes without plugging the holes. The coated parts may be used as microelectronic connection components such as chip carriers used in packaging semiconductor chips.

公开(公告)号：US06501031B1

公开(公告)日：2002-12-31

申请号：US09655809

申请日：2000-09-06

Applicant: Andrew Z. Glovatsky ,  Jay D. Baker ,  Robert Edward Belke ,  Myron Lemecha ,  Richard Keith McMillan ,  Thomas B. Krautheim

Inventor： Andrew Z. Glovatsky ,  Jay D. Baker ,  Robert Edward Belke ,  Myron Lemecha ,  Richard Keith McMillan ,  Thomas B. Krautheim

IPC: H05K111

CPC classification number: H05K3/445 ,  H05K3/386 ,  H05K3/4038 ,  H05K3/4092 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09554 ,  H05K2201/09581 ,  H05K2203/1438 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49172

Abstract: A multi-layer electronic circuit board design 10 having a core member 12, a pair of dielectric layers 14, 16 disposed thereon, and a first circuit portion 20 which is coupled to the dielectric layer 14 and core member 12 using a layer of adhesive material 18. Circuit board design 10 further having selectively formed “blind” apertures, vias or cavities 22 formed through the first circuit portion 20, dielectric layer 14, and adhesive layer 18, thereby exposing core member 12.

Abstract translation: 具有芯构件12，设置在其上的一对电介质层14,16的多层电子电路板设计10以及使用粘合材料层连接到电介质层14和芯构件12的第一电路部分20 电路板设计10还具有选择性地形成通过第一电路部分20形成的“盲”孔，通孔或空腔22，电介质层14和粘合层18，从而露出芯构件12。

公开(公告)号：US20020137347A1

公开(公告)日：2002-09-26

申请号：US09815226

申请日：2001-03-22

Inventor： Bharat Z. Patel ,  Jay D. Baker ,  Lakhi N. Goenka ,  Michael Allen Howey ,  Mohan R. Paruchuri ,  Richard Keith McMillan

IPC: H01L021/311

CPC classification number: H05K3/44 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/429 ,  H05K3/445 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0361 ,  H05K2201/0397 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/0733 ,  H05K2203/1184

Abstract: A method 10 for making a multi-layer circuit board 70 having at least one electrically conductive interconnection portion or nullvianull 72 which extends within the board 70 and at least one air-bridge 74. The method 10 includes the steps of forming protuberances 13 upon a core member 12, attaching pre-circuit assemblies 32, 34 to the core member 12, thereby forming the circuit board 70 while concomitantly and selectively extending at least one of the protuberances 13 within the formed circuit board 70.

Abstract translation: 制造多层电路板70的方法10具有至少一个在板70内和至少一个空气桥74上延伸的导电互连部分或“通孔”72。方法10包括以下步骤：形成突起13 在芯构件12上，将预电路组件32,34附接到芯构件12，从而形成电路板70，同时并且选择性地延伸形成的电路板70内的至少一个突起13。