公开(公告)号：US20080179721A1

公开(公告)日：2008-07-31

申请号：US11669880

申请日：2007-01-31

Applicant: Cheng-Lien Chiang

Inventor： Cheng-Lien Chiang

IPC: H01L23/495 ,  H01L23/48

CPC classification number: H05K1/144 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/48 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/10666 ,  H05K2203/0455 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A transfer carrier comprising a transfer substrate, two aperture arrays, a contact pattern and a semiconductor device. The transfer substrate located on the opposed sides of the transfer substrate to define a cavity on the transfer substrate, the aperture arrays has a top surface and a bottom surface. The two aperture arrays have apertures extending from the top surface through to the bottom surface. The apertures have conductive layers formed on the inner surfaces of the apertures. The contact pattern is located with contacts lo electrically connected to the corresponding conductive layer of the apertures. The semiconductor device has pads arranged in identical pattern as the contact pattern, the semiconductor device being electrically connected to the contacts. The transfer carrier is also manufactured as an integrated circuit package. The transfer carriers and integrated circuit packages are stacked via solder connections.

Abstract translation: 一种转印载体，包括转印衬底，两个孔阵列，接触图案和半导体器件。 转印基板位于转印基板的相对侧上以限定转印基板上的空腔，孔阵列具有顶表面和底表面。 两个孔阵列具有从顶表面延伸到底表面的孔。 这些孔具有形成在孔的内表面上的导电层。 接触图案定位为具有电连接到孔的相应导电层的触点。 半导体器件具有以与接触图案相同的图案排列的衬垫，半导体器件电连接到触点。 转印载体也作为集成电路封装制造。 传输载体和集成电路封装通过焊料连接堆叠。

公开(公告)号：US20080173469A1

公开(公告)日：2008-07-24

申请号：US12000730

申请日：2007-12-17

Applicant: Eiichi Hirakawa

Inventor： Eiichi Hirakawa

IPC: H05K1/02

CPC classification number: H05K1/0219 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09609 ,  H05K2201/09672 ,  H05K2201/10674

Abstract: A multilayer wiring board having a structure in which wiring layers 12A to 12D and insulating layers 11A to 11C are alternately arranged, and in which one or plural kinds of wirings selected from a group of a signal wiring 25 having a signal electrode 15, a power supply wiring 26 having a power supply electrode 16, and a ground wiring 27 having a ground electrode 17 are formed on each of the wiring layers 12A to 12D. The signal wiring 25 and the power supply wiring 26 are alternately provided on the insulating layers. Alternatively, the signal wiring 25 and the ground wiring 27 are alternately provided on the insulating layers.

Abstract translation: 具有布线层12A〜12D和绝缘层11A〜11C的结构的多层布线基板交替布置，并且其中选自一组或多种布线，其中信号布线25具有信号电极 如图15所示，在每个布线层12A至12D上形成具有电源电极16的电源布线26和具有接地电极17的接地布线27.信号布线25和电源布线26交替 设置在绝缘层上。 或者，信号布线25和接地布线27交替地设置在绝缘层上。

公开(公告)号：US20080110666A1

公开(公告)日：2008-05-15

申请号：US11936973

申请日：2007-11-08

Applicant: Tsutomu OOTA

Inventor： Tsutomu OOTA

IPC: H05K1/00

CPC classification number: H05K1/0224 ,  H05K1/0253 ,  H05K1/0393 ,  H05K2201/09609 ,  H05K2201/09681

Abstract: A base layer of a bent portion of a FPC is formed on the front side thereof with second ground bent lines arranged in a mesh pattern and third ground bent lines intersecting with the second ground bent lines in a lateral direction, and on the back side thereof with first ground bent lines along the bending direction. The first ground bent lines are electrically connected to the second ground bent lines and the third ground bent lines via through holes.

Abstract translation: FPC的弯曲部的基层在其前侧形成有以网格图案布置的第二接地弯曲线和在第二接地弯曲线与横向方向相交的第三接地弯曲线，并且在其背面上形成 沿着弯曲方向的第一根弯曲的线。 第一接地弯曲线通过通孔电连接到第二接地弯曲线和第三接地弯曲线。

公开(公告)号：US07329818B2

公开(公告)日：2008-02-12

申请号：US11201104

申请日：2005-08-11

Applicant: Tsutomu Matsuo

Inventor： Tsutomu Matsuo

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K1/116 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/18 ,  H05K3/429 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/10189 ,  H01L2924/00

Abstract: In a transmission circuit board, ground terminal portions (10) are disposed at every other two rows in both end columns. Each of signal circuit layers (20) includes at least a pair of adjacent signal connecting portions electrically connected to a pair of the wiring portions (21, 22) arranged in parallel in a row direction and the column direction different from those on an adjacent signal circuit layer. Each of the ground layers is electrically connected to at least one of the ground terminal portions (10) in the both end columns.

Abstract translation: 在传输电路板中，接地端子部分（10）在两个端部列中每隔两列设置。 每个信号电路层（20）至少包括一对相邻的信号连接部分，电连接到沿着行方向并联布置的一对布线部分（21,22），并且列方向与相邻信号上的列方向不同 电路层。 每个接地层电连接到两端列中的至少一个接地端子部分（10）。

公开(公告)号：US20070226998A1

公开(公告)日：2007-10-04

申请号：US11760217

申请日：2007-06-08

Applicant: Kevin Olson ,  Alan Wang

Inventor： Kevin Olson ,  Alan Wang

IPC: H05K3/10 ,  H01L23/495

CPC classification number: H01L21/486 ,  C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/142 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  H01L2924/00

Abstract: Processes for fabricating a multi-layer circuit assembly and a multi-layer circuit assembly fabricated by such processes are provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias, these area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; and (c) applying a layer of metal to all surfaces of the substrate. Additional processing steps such as circuitization may be included.

Abstract translation: 提供了用于制造多层电路组件的工艺和通过这些工艺制造的多层电路组件。 该方法包括（a）提供基底，其至少一个区域包括多个通孔，这些区域的通孔密度为500至10,000个孔/平方英寸（75至1550个孔/平方厘米）; （b）将介电涂层施加到所述基底的所有暴露表面上以在其上形成保形涂层; 和（c）在基片的所有表面上涂一层金属。 可以包括诸如电路化的附加处理步骤。

公开(公告)号：US20070224737A1

公开(公告)日：2007-09-27

申请号：US11385271

申请日：2006-03-21

Applicant: Carl Berlin ,  Deepukumar Nair ,  Matthew Walsh

Inventor： Carl Berlin ,  Deepukumar Nair ,  Matthew Walsh

IPC: H01L21/20

CPC classification number: H01P1/203 ,  H01P1/2005 ,  H05K1/0233 ,  H05K1/0236 ,  H05K3/4069 ,  H05K2201/0215 ,  H05K2201/086 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2203/0557 ,  H05K2203/104 ,  H05K2203/171

Abstract: Tuned Electromagnetic Bandgap (EBG) devices, and a method for making and tuning tuned EBG devices are provided. The method includes the steps of providing first and second overlapping substrates, placing magnetically alignable conductive material between the substrates, and applying a magnetic field in the vicinity of the magnetically alignable conductive material to align at least some of the material into conductive vias. The method further includes the steps of physically altering via characteristics of EBG devices to tune the bandpass and resonant frequencies of the EBG devices.

Abstract translation: 提供了调谐电磁带隙（EBG）器件，以及用于制造和调谐调谐EBG器件的方法。 该方法包括以下步骤：提供第一和第二重叠基板，将磁性取向的导电材料放置在基板之间，以及在可磁对准导电材料附近施加磁场，使至少一些材料对准导电通孔。 该方法还包括通过EBG器件的特性物理地改变以调节EBG器件的带通和谐振频率的步骤。

公开(公告)号：US07262368B2

公开(公告)日：2007-08-28

申请号：US10917978

申请日：2004-08-13

Applicant: Belgacem Haba ,  Masud Beroz ,  David B. Tuckerman ,  Giles Humpston ,  Richard Dewitt Crisp

Inventor： Belgacem Haba ,  Masud Beroz ,  David B. Tuckerman ,  Giles Humpston ,  Richard Dewitt Crisp

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H01L23/49838 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/041 ,  H05K3/06 ,  H05K3/202 ,  H05K3/4038 ,  H05K2201/09609 ,  H05K2201/097 ,  H05K2201/09827 ,  H05K2201/09881 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Provided are connection structures for a microelectronic device and methods for forming the structure. A substrate is included having opposing surfaces and a plurality of holes extending through the surfaces. Also included is a plurality of electrically conductive posts. Each post extends from a base to a tip located within a corresponding hole of the substrate. An additional substrate may be provided such that the base of each post is located on a surface thereof. Additional electrically conductive posts may be provided having tips in corresponding holes of the additional substrate. Optionally, a dielectric material may be placed between the substrate and the posts.

Abstract translation: 提供了用于微电子器件的连接结构和用于形成结构的方法。 包括具有相对表面的基板和延伸穿过该表面的多个孔。 还包括多个导电柱。 每个柱从基部延伸到位于基板的相应孔内的尖端。 可以提供另外的基底，使得每个柱的基部位于其表面上。 可以提供额外的导电柱，其具有在附加衬底的相应孔中的尖端。 可选地，介电材料可以放置在基板和柱之间。

公开(公告)号：US07239527B1

公开(公告)日：2007-07-03

申请号：US11009408

申请日：2004-12-08

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01R12/16

CPC classification number: H05K1/0237 ,  H05K1/0219 ,  H05K1/0225 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09609 ,  H05K2201/09663

Abstract: For electrical backplanes and the like, a power plane adaptation to improve the propagation of high-speed signals through clearances in an embedded power plane is disclosed. In exemplary embodiments, the power plane is segmented in a high-speed connector region, such that a portion of the metal layer that forms the power plane is retained in the high-speed connector region—but isolated from the power-delivery portion of the power plane. The isolated portion is connected to digital ground, and clearances are formed therein where high-speed signaling throughholes will pass through the region. In some embodiments, various attainable advantages include better manufacturability, better matching and control of high-speed signaling throughhole impedance, and improved noise isolation. Other embodiments are described and claimed.

Abstract translation: 对于电气背板等，公开了一种用于改善高速信号通过嵌入式电源平面中的间隙的传播的电力平面适配。 在示例性实施例中，电力平面在高速连接器区域中分段，使得形成电力平面的金属层的一部分保持在高速连接器区域中，但是与电力输送部分 电力飞机 隔离部分连接到数字地，并且在其中形成间隙，其中高速信令通孔将通过该区域。 在一些实施例中，各种可获得的优点包括更好的可制造性，更好地匹配和控制高速信号通孔阻抗以及改进的噪声隔离。 描述和要求保护其他实施例。

公开(公告)号：US20070029106A1

公开(公告)日：2007-02-08

申请号：US10551439

申请日：2004-04-06

Applicant: Shinobu Kato

Inventor： Shinobu Kato

IPC: H05K1/11

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0263 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09609 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: In a core substrate 30, a ground through hole 36E and a power through hole 36P are disposed in the grid formation, so that electromotive force induced in X direction and Y direction cancel out each other. As a result, even if mutual inductance is reduced and a high frequency IC chip is loaded, electric characteristic and reliability can be improved without generating malfunction or error.

Abstract translation: 在芯基板30中，在栅格形成中配置有通孔36E和通电孔36P，使得在X方向和Y方向上感应的电动势彼此抵消。 结果，即使减小互感并且加载高频IC芯片，也可以提高电特性和可靠性而不产生故障或错误。

公开(公告)号：US07042083B2

公开(公告)日：2006-05-09

申请号：US10756507

申请日：2004-01-14

Applicant: Yoshiaki Sugizaki ,  Hiroshi Ikebe

Inventor： Yoshiaki Sugizaki ,  Hiroshi Ikebe

IPC: H01L23/12

CPC classification number: H01L23/49822 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/0133 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/19043 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/0271 ,  H05K1/056 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09609 ,  H05K2201/09681 ,  H01L2924/01025 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides a package substrate which comprises a substrate defined by top and bottom surfaces and having a plurality of perforations; a resin insulation layer configured to implement a multi-level structure disposed on both surfaces of the substrate; a built-up wiring layer implementing the multi-level structure disposed on the resin insulation layer on both surfaces of the substrate; and a semiconductor chip mounting region provided on the top or the bottom surface of the substrate; wherein, a perforation exists on any straight line connecting from the center of the substrate to an arbitrary point on a periphery of the substrate.

Abstract translation: 本发明提供了一种封装基板，其包括由顶表面和底表面限定并具有多个穿孔的基板; 树脂绝缘层，被配置为实现设置在所述基板的两个表面上的多层结构; 实现设置在基板的两个表面上的树脂绝缘层上的多层结构的积层布线层; 以及设置在基板的顶面或底面上的半导体芯片安装区域; 其中，在从基板的中心连接到基板的周边上的任意点的任何直线上存在穿孔。