公开(公告)号：US08289099B2

公开(公告)日：2012-10-16

申请号：US12568362

申请日：2009-09-28

Applicant: Han Kim ,  Ja-Bu Koo ,  Dae-Hyun Park

Inventor： Han Kim ,  Ja-Bu Koo ,  Dae-Hyun Park

IPC: H03H7/00

CPC classification number: H01P1/2005 ,  H01P1/203 ,  H05K1/0236 ,  H05K2201/09309 ,  H05K2201/09627 ,  H05K2201/09681

Abstract: An electromagnetic bandgap structure includes: first conductive plates, placed on a first planar surface, in which the first conductive plates are lined up in a first direction; second conductive plates, placed on a second planar surface and arranged at an area corresponding to an area in which the first conductive plates are disposed, in which the second conductive plates are lined up in the first direction; a first stitching via, electrically connecting any two adjacent conductive portions with each other and in which the two adjacent conductive portions are lined up in a direction that is different from the first direction on the first planar surface; and a second stitching via, electrically connecting any two adjacent conductive portions with each other and in which the two adjacent conductive portions are lined up in a direction that is different from the first direction on the second planar surface.

Abstract translation: 电磁带隙结构包括：第一导电板，放置在第一平面上，第一导电板沿第一方向排列; 第二导电板，放置在第二平坦表面上并且布置在与设置有第一导电板的区域相对应的区域中，其中第二导电板沿第一方向排列; 第一缝合通孔，将任何两个相邻的导电部分彼此电连接，并且其中两个相邻的导电部分沿与第一平坦表面上的第一方向不同的方向排列; 以及第二缝合通孔，将任何两个相邻的导电部彼此电连接，并且其中两个相邻的导电部分在与第二平面上的第一方向不同的方向上排列。

公开(公告)号：US08222540B2

公开(公告)日：2012-07-17

申请号：US12775916

申请日：2010-05-07

Applicant: Akiyoshi Saitou

Inventor： Akiyoshi Saitou

IPC: H05K1/11

CPC classification number: H05K1/0251 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0242 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/09627 ,  H05K2201/0979 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A printed wiring board having an insulating core; a plurality of vias having axes parallel to and at equal distance from a reference axis and passing through the core; a first conductive film formed on a front surface of the core from the reference axis to each of the individual vias; a first insulating film stacked on the front surface of the core and covering the first conductive film; a first connecting via having an axis identical to the reference axis and passing through the first stacked film; a second conductive film formed on a back surface of the core from the reference axis to each of the individual vias; a second insulating film stacked on the back surface of the core and covering the second conductive film; and a second connecting via having an axis identical to the reference axis and passing through the second stacked film.

Abstract translation: 一种具有绝缘芯的印刷线路板; 多个通孔具有平行于参考轴线并且距离参考轴线等距离并且穿过芯部的轴线; 第一导电膜，其形成在所述芯的前表面上，从参考轴线到每个所述各个通孔; 第一绝缘膜，堆叠在所述芯的前表面上并覆盖所述第一导电膜; 第一连接通孔，其具有与参考轴线相同的轴线并穿过第一层叠膜; 形成在所述芯的背面上的第二导电膜，所述第二导电膜从所述参考轴线到每个所述各个通孔; 层叠在所述芯的背面上并覆盖所述第二导电膜的第二绝缘膜; 以及第二连接通孔，其具有与参考轴线相同的轴线并且穿过第二层叠膜。

公开(公告)号：US08153906B2

公开(公告)日：2012-04-10

申请号：US11986323

申请日：2007-11-20

Applicant: Hsiuan-ju Hsu ,  Richard Walter Ziolkowski

Inventor： Hsiuan-ju Hsu ,  Richard Walter Ziolkowski

IPC: H05K1/11

CPC classification number: H05K1/11 ,  H01R12/52 ,  H01R13/6585 ,  H05K1/0219 ,  H05K3/4602 ,  H05K2201/09627 ,  H05K2201/09809 ,  Y10T29/49002

Abstract: The embodiment of the invention is about a novel interconnection structure which can be incorporated into a variety of connectors, as well as other types of interconnections in order to reduce crosstalk, to improve signal integrity and to achieve EM emission compliance. A 4-via (2 signal vias, 1 power via, and 1 ground via) interconnection structure was used for demonstrating the effect of the novel interconnection structure. The same concept can be applied to any multi-via and multi-layer interconnection structure such as PCB, IC packaging circuit, or die circuit. Vias that have an electrical property can be added adjacent to the basic 4-via interconnection structure to achieve a multi-via interconnection structure. For 1-via (1 signal via or 1 power via), 2-via (1 signal via and 1 ground via or 1 signal via and 1 power via) and 3-via (1 signal via, 1 ground via, and 1 power via) interconnection structure, the proposed interconnection structure based upon the same concept can be applied as well.

Abstract translation: 本发明的实施例涉及一种新颖的互连结构，其可并入到各种连接器以及其它类型的互连中，以便减少串扰，提高信号完整性并实现EM发射顺应性。 使用4通道（2个信号通孔，1个电源通孔和1个通孔）互连结构来证明新型互连结构的效果。 相同的概念可以应用于诸如PCB，IC封装电路或裸片电路的任何多通孔和多层互连结构。 具有电性能的通孔可以邻近基本的4通孔互连结构添加，以实现多通孔互连结构。 对于1通（1个通道或1个电源通孔），2通（1个通道和1个通路或1个通道和1个电源通孔）和3通（1个信号通孔，1个通路和1个电源 通过）互连结构，也可以应用基于相同概念的所提出的互连结构。

公开(公告)号：US08144300B2

公开(公告)日：2012-03-27

申请号：US12197524

申请日：2008-08-25

Applicant: Kyoung-Soo Kim ,  Jin-Ho Park

Inventor： Kyoung-Soo Kim ,  Jin-Ho Park

IPC: G02F1/1345

CPC classification number: H05K1/183 ,  G02F1/13452 ,  H05K1/114 ,  H05K3/341 ,  H05K3/429 ,  H05K2201/09072 ,  H05K2201/09518 ,  H05K2201/09627 ,  H05K2201/10189 ,  H05K2201/10969 ,  H05K2201/2072

Abstract: A printed circuit board on which a connector is mounted includes a conductive layer, insulating layers, and a supporting member. A part of the conductive layer is exposed on a top surface of the PCB in order to form a connecting pad portion for connecting the connector. The insulating layers are disposed proximate to both sides of the conductive layer. The supporting member is connected to the conductive layer and covers a surface of a hole formed by opening an orifice through the conductive layer and the insulating layer. The hole is disposed adjacent to the connecting pad portion.

Abstract translation: 其上安装有连接器的印刷电路板包括导电层，绝缘层和支撑构件。 导电层的一部分露出在PCB的顶表面上，以便形成用于连接连接器的连接焊盘部分。 绝缘层靠近导电层的两侧设置。 支撑构件连接到导电层并覆盖通过导电层和绝缘层打开孔而形成的孔的表面。 孔邻近连接焊盘部分设置。

公开(公告)号：US20120055016A1

公开(公告)日：2012-03-08

申请号：US13292674

申请日：2011-11-09

Applicant: Dan Gorcea

Inventor： Dan Gorcea

IPC: H01K3/10

CPC classification number: H05K1/0248 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09336 ,  H05K2201/09627 ,  H05K2201/0979 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/31511

Abstract: In accordance with a first embodiment, the present invention provides a circuit substrate comprising a first surface; a second surface; a first via having a first end near said first surface and a second end near said second surface; a second via having a first end near said first surface and a second end near said second surface; a first conductive element electrically coupling said first end of said first via and said first end of said second via; a second conductive element electrically coupling said second end of said first via and said second end of said second via; an input signal line coupled to said first via; and an output signal line coupled to said second via.

Abstract translation: 根据第一实施例，本发明提供了一种包括第一表面的电路基板; 第二表面 具有靠近所述第一表面的第一端和靠近所述第二表面的第二端的第一通孔; 第二通孔，其具有靠近所述第一表面的第一端和靠近所述第二表面的第二端; 电连接所述第一通孔的所述第一端和所述第二通孔的所述第一端的第一导电元件; 电连接所述第一通孔的所述第二端和所述第二通孔的所述第二端的第二导电元件; 耦合到所述第一通孔的输入信号线; 以及耦合到所述第二通孔的输出信号线。

公开(公告)号：US20110278951A1

公开(公告)日：2011-11-17

申请号：US13194383

申请日：2011-07-29

Applicant: Takeshi KURIHARA ,  Keiichi ICHIKAWA

Inventor： Takeshi KURIHARA ,  Keiichi ICHIKAWA

IPC: H01F38/14

CPC classification number: H02J50/10 ,  H01F38/14 ,  H02J5/005 ,  H02J7/025 ,  H02J50/12 ,  H02J50/70 ,  H05K1/0216 ,  H05K1/0265 ,  H05K1/115 ,  H05K2201/0792 ,  H05K2201/09627 ,  H05K2201/097 ,  H05K2201/0979 ,  H05K2201/1003 ,  H05K2201/10166

Abstract: The disclosure provides a non-contact power receiving apparatus including a conductive pattern in a second region of a substrate not covered by a magnetic sheet. The conductive pattern includes first and second electrodes provided in a first plane parallel to a surface of the substrate and arranged in a length direction of the conductive pattern. A third electrode is formed on a second plane parallel with the first plane. A first via hole connects superposed portions of the first and third electrodes to each other, and a second via hole connects superposed portions of the second and third electrodes to each other. As a result, loops of eddy currents generated in the conductive pattern can be made to be small, whereby eddy current loss can be reduced.

Abstract translation: 本公开提供一种非接触式电力接收装置，其包括在未被磁性片覆盖的基板的第二区域中的导电图案。 导电图案包括设置在与基板的表面平行的第一平面中并沿导电图案的长度方向布置的第一和第二电极。 第三电极形成在与第一平面平行的第二平面上。 第一通孔将第一和第三电极的叠置部彼此连接，第二通孔将第二电极和第三电极的叠置部彼此连接。 结果，可以使在导电图案中产生的涡流的回路小，从而可以减小涡流损耗。

公开(公告)号：US08027170B2

公开(公告)日：2011-09-27

申请号：US12340965

申请日：2008-12-22

Applicant: Kazuo Hattori ,  Isamu Fujimoto

Inventor： Kazuo Hattori ,  Isamu Fujimoto

IPC: H05K7/00

CPC classification number: H05K1/0231 ,  H01G4/35 ,  H05K1/113 ,  H05K2201/09627

Abstract: An electronic device which includes a feedthrough capacitor mounted on a front surface of a substrate. A feedthrough electrode penetrates a laminate (body of the capacitor). External electrodes are electrically connected to opposite ends of the feedthrough electrode. A capacitor electrode is disposed to form capacity in cooperation with the feedthrough electrode. A wiring conductor is formed on a rear surface of the substrate or inside the substrate, and via-hole conductors are connected to the wiring conductor. The feedthrough electrode and the external electrodes constitute a first current path. The wiring conductor and the via-hole conductors constitute a second current path electrically connected in parallel to the first current path.

Abstract translation: 一种电子装置，其包括安装在基板的前表面上的穿通电容器。 穿通电极穿透层压体（电容器体）。 外部电极电连接到馈通电极的相对端。 配置电容器电极以与馈通电极协作形成容量。 布线导体形成在基板的背面或基板的内部，通孔导体与布线导体连接。 馈通电极和外部电极构成第一电流路径。 布线导体和通孔导体构成与第一电流路并联电连接的第二电流路径。

公开(公告)号：US08003896B2

公开(公告)日：2011-08-23

申请号：US11832673

申请日：2007-08-02

Applicant: Youhong Wu

Inventor： Youhong Wu

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multi-layer printed wiring board has a core substrate, a first interlayer insulation layer formed over the core substrate, a first filled via formed in the first interlayer insulation layer, a second interlayer insulation layer formed over the first interlayer insulation layer, and a second filled via formed in the second interlayer insulation layer. The first filled via has a bottom portion having a first diameter. The second filled via has a bottom portion having a second diameter smaller than the first diameter.

Abstract translation: 多层印刷线路板具有芯基板，形成在芯基板上的第一层间绝缘层，形成在第一层间绝缘层中的第一填充通孔，形成在第一层间绝缘层上的第二层间绝缘层，以及 第二填充通孔形成在第二层间绝缘层中。 第一填充通孔具有第一直径的底部。 第二填充通孔具有第二直径小于第一直径的底部。

公开(公告)号：US07977582B2

公开(公告)日：2011-07-12

申请号：US12020643

申请日：2008-01-28

Applicant: Mark G. Clark ,  John R. Dangler ,  Matthew S. Doyle ,  Thomas D. Kidd ,  Timothy L. McMillan ,  Jason T. Stoll

Inventor： Mark G. Clark ,  John R. Dangler ,  Matthew S. Doyle ,  Thomas D. Kidd ,  Timothy L. McMillan ,  Jason T. Stoll

IPC: H05K1/11

CPC classification number: H05K1/0219 ,  H05K1/0393 ,  H05K3/429 ,  H05K2201/0715 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/10189 ,  Y10T29/49124 ,  Y10T29/49165

Abstract: A flexible multilayer printed circuit assembly with shield fences. The flexible multilayer printed circuit assembly with multiple conductive layers includes logic ground vias that connect logic ground plane layers together, and shield vias that connect a top and a bottom shield plane layer together. Each of the shield fences is formed between the shield vias on an outside perimeter of each of the conductive layers. Each of the shield fences contains the logic ground vias inside, and also contains each corresponding conductive layer in the horizontal direction to which each layer extends.

Abstract translation: 具有屏蔽栅栏的柔性多层印刷电路组件。 具有多个导电层的柔性多层印刷电路组件包括将逻辑接地平面层连接在一起的逻辑接地通孔，以及将顶部和底部屏蔽平面层连接在一起的屏蔽通孔。 每个屏蔽栅栏形成在每个导电层的外周边上的屏蔽通孔之间。 每个屏蔽围栏都包含内部的逻辑接地孔，并且还包含每个层延伸的水平方向上的每个对应的导电层。

公开(公告)号：US20110067914A1

公开(公告)日：2011-03-24

申请号：US12654361

申请日：2009-12-17

Applicant: Hyo-Jic Jung ,  Han Kim ,  Mi-Ja Han ,  Kang-Wook Bong ,  Dae-Hyun Park

Inventor： Hyo-Jic Jung ,  Han Kim ,  Mi-Ja Han ,  Kang-Wook Bong ,  Dae-Hyun Park

IPC: H05K9/00 ,  H05K1/11

CPC classification number: H05K1/0236 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K2201/09309 ,  H05K2201/09627 ,  H01L2924/00014

Abstract: Disclosed is a printed circuit board into which an electromagnetic bandgap structure for blocking a noise is inserted. The electromagnetic bandgap structure can include a first conductor and a second conductor arranged on different planar surfaces, a third conductor arranged on a same planar surface that is different from a planar surface where the second conductor is arranged, and a first stitching via unit configured to connect the first conductor to the third connector through the planar surface where the second conductor is arranged and being electrically separated from the second conductor. The first conductor can include a first plate, a second plate spaced from the first plate, and a second stitching unit configured to electrically connect the first plate to the second plate through a planar surface that is different from a planar surface where the first plate and the second plate are arranged.

Abstract translation: 公开了一种印刷电路板，其中插入用于阻挡噪声的电磁带隙结构。 电磁带隙结构可以包括布置在不同平面上的第一导体和第二导体，布置在与布置第二导体的平面不同的相同平面上的第三导体，以及第一缝合通孔单元， 通过布置第二导体的平面表面将第一导体连接到第三连接器，并与第二导体电分离。 第一导体可以包括第一板，与第一板间隔开的第二板，以及第二缝合单元，其被配置为通过与第一板和第二板的平坦表面不同的平面表面将第一板电连接到第二板 布置第二板。