公开(公告)号：US20100084178A1

公开(公告)日：2010-04-08

申请号：US12247577

申请日：2008-10-08

Applicant: Michael Francis Sweeney ,  Jorge Eduardo Martinez-Vargas, JR. ,  Michael Clifford Freda

Inventor： Michael Francis Sweeney ,  Jorge Eduardo Martinez-Vargas, JR. ,  Michael Clifford Freda

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H05K1/116 ,  H05K1/113 ,  H05K3/3421 ,  H05K3/3447 ,  H05K2201/09472 ,  H05K2201/0959 ,  H05K2201/09845 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A via is provided on a printed circuit board with at least one additional depression encompassing the via, such that the via passes through a portion of the depression. Solder can pool in the depression, allowing for a stronger mechanical bond and eliminating many issues with respect to a lack of coplanarity between a lead and the printed circuit board. The depression can be provided with plugged and unplugged vias, and improves the mountings associated with both.

Abstract translation: 通孔在印刷电路板上设置有至少一个包围通孔的附加凹部，使得通孔穿过凹陷部分。 焊料可以集中在凹陷中，允许更强的机械粘合，并消除了铅和印刷电路板之间缺乏共面性的许多问题。 凹陷可以提供堵塞和拔下的通孔，并改善与两者相关联的安装。

公开(公告)号：US20100078210A1

公开(公告)日：2010-04-01

申请号：US12286626

申请日：2008-10-01

Applicant: Vincent C. Korthuis

Inventor： Vincent C. Korthuis

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K3/4685 ,  G02F1/167 ,  G02F2001/1672 ,  H05K3/005 ,  H05K3/107 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2203/0108 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155

Abstract: A method of manufacturing a microelectronic device including imprinting a layer on a substrate with an imprinted pattern, the imprinted pattern defining a first anchor impression within the layer that includes a first base region positioned adjacent the layer and a first distal region positioned opposite the first base region, the first distal region defining a cross sectional area greater than a cross sectional area of the first base region, and the imprinted pattern defining a second anchor impression within the layer that includes a second base region positioned adjacent the layer and a second distal region positioned opposite the second base region, the second distal region defining a cross sectional area greater than a cross sectional area of the second base region and greater than a cross sectional area of the first distal region.

Abstract translation: 一种制造微电子器件的方法，包括用印迹图案在基片上刻印一层，该刻印图案限定该层内的第一锚定印模，该第一锚定印模包括邻近该层定位的第一基底区域和与第一基底相对定位的第一远侧区域 区域，所述第一远侧区域限定大于所述第一基底区域的横截面面积的横截面积，并且所述印刷图案限定所述层内的第二锚定印模，所述第二锚定印模包括邻近所述层定位的第二基底区域和第二远侧区域 与所述第二基部区域相对定位，所述第二远侧区域限定大于所述第二基底区域的横截面面积的横截面面积，并且大于所述第一远侧区域的横截面面积。

公开(公告)号：US20100065962A1

公开(公告)日：2010-03-18

申请号：US12624622

申请日：2009-11-24

Applicant: Reinhold Bayerer ,  Thomas Hunger

Inventor： Reinhold Bayerer ,  Thomas Hunger

IPC: H01L23/15 ,  H05K1/03 ,  H05K3/10

CPC classification number: H01L23/3735 ,  H01L23/3731 ,  H01L23/3736 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/072 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48699 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/0256 ,  H05K1/0306 ,  H05K1/053 ,  H05K3/4046 ,  H05K3/4061 ,  H05K3/44 ,  H05K3/462 ,  H05K3/4629 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/0379 ,  H05K2201/09145 ,  H05K2201/09554 ,  H05K2201/09845 ,  H05K2201/10234 ,  H01L2224/8382 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2224/83205 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor module includes a multilayer substrate. The multilayer substrate includes a first metal layer and a first ceramic layer over the first metal layer. An edge of the first ceramic layer extends beyond an edge of the first metal layer. The multilayer substrate includes a second metal layer over the first ceramic layer and a second ceramic layer over the second metal layer. An edge of the second ceramic layer extends beyond an edge of the second metal layer. The multilayer substrate includes a third metal layer over the second ceramic layer.

Abstract translation: 半导体模块包括多层基板。 多层基板包括第一金属层和第一金属层上的第一陶瓷层。 第一陶瓷层的边缘延伸超过第一金属层的边缘。 多层基板包括在第一陶瓷层之上的第二金属层和在第二金属层上的第二陶瓷层。 第二陶瓷层的边缘延伸超过第二金属层的边缘。 多层基板包括在第二陶瓷层上的第三金属层。

公开(公告)号：US07675176B2

公开(公告)日：2010-03-09

申请号：US11968035

申请日：2007-12-31

Applicant: Chang-Yong Park ,  Kwang-Ho Chun ,  Dong-Chun Lee ,  Yong-Hyun Kim

Inventor： Chang-Yong Park ,  Kwang-Ho Chun ,  Dong-Chun Lee ,  Yong-Hyun Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/111 ,  H01L2924/0002 ,  H05K3/3452 ,  H05K2201/0367 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09845 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: Provided are a semiconductor package and a module printed circuit board (PCB) for mounting the same. Each of the semiconductor package and the module PCB includes a substrate, a first-type pad structure disposed in a first region of the substrate, and a second-type pad structure disposed in a second region of the package substrate. The first-type pad includes a first conductive pad disposed on the package substrate and a first insulating layer coated on the package substrate. The first insulating layer has a first opening by which a portion of a sidewall of the first conductive pad is exposed, and partially covers the first conductive pad. The second-type pad includes a second insulating layer coated on the package substrate to have a second opening and a second conductive pad disposed on the package substrate in the second opening to have an exposed sidewall. In this structure, the semiconductor package and the module PCB can have an excellent resistance to physical and thermal stresses to enhance structural reliability.

Abstract translation: 提供了用于安装它的半导体封装和模块印刷电路板（PCB）。 半导体封装和模块PCB中的每一个包括衬底，设置在衬底的第一区域中的第一类型衬垫结构以及设置在封装衬底的第二区域中的第二类型衬垫结构。 第一型焊盘包括设置在封装衬底上的第一导电焊盘和涂覆在封装衬底上的第一绝缘层。 第一绝缘层具有第一开口，通过该第一开口，第一导电焊盘的侧壁的一部分被暴露，并且部分覆盖第一导电焊盘。 第二类型衬垫包括涂覆在封装衬底上以具有第二开口的第二绝缘层和设置在第二开口中的封装衬底上的具有暴露侧壁的第二导电焊盘。 在这种结构中，半导体封装和模块PCB可以具有优异的耐物理和热应力，以增强结构可靠性。

公开(公告)号：US20100054671A1

公开(公告)日：2010-03-04

申请号：US12559637

申请日：2009-09-15

Applicant: Takuma BAN ,  Yasunobu MATSUOKA

Inventor： Takuma BAN ,  Yasunobu MATSUOKA

IPC: G02B6/36

CPC classification number: G02B6/43 ,  H01L31/0203 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0274 ,  H05K1/141 ,  H05K1/183 ,  H05K2201/049 ,  H05K2201/09845 ,  H05K2201/10727 ,  H05K2203/167 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A structure which is able to stably achieve electrical coupling, and which is capable of efficient optical coupling is provided. Optical coupling is achieved with the lower surface of an opto-electric package and the upper surface of an opto-electric hybrid board. On the other hand, electrical connection is achieved by means of contact between electrodes on the side surfaces of the opto-electric package and electrodes on the inner-wall side surfaces of a socket mounted on the opto-electric hybrid board. The electrodes are in electrical contact with electrical wiring.

Abstract translation: 提供能够稳定地实现电耦合并且能够有效地进行光耦合的结构。 通过光电封装的下表面和光电混合板的上表面实现光耦合。 另一方面，通过光电封装的侧面的电极与安装在光电混合基板上的插座的内壁侧面的电极之间的接触来实现电连接。 电极与电气线路电接触。

公开(公告)号：US07659727B2

公开(公告)日：2010-02-09

申请号：US12072704

申请日：2008-02-27

Applicant: Yoshiyuki Fukami

Inventor： Yoshiyuki Fukami

IPC: G01R31/02 ,  G01R27/26

CPC classification number: G01R31/2812 ,  G01R31/2805 ,  H05K1/0268 ,  H05K1/0306 ,  H05K1/117 ,  H05K3/4605 ,  H05K2201/09845

Abstract: A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. One of the conductor layers has a grounded pattern. Each of the conductor layers has a reference pattern, which is usable as a standard in calculation of an electric capacitance. An electric capacitance is measured between the grounded pattern and the three-dimensional wiring path. On the other hand, a theoretical electrical capacitance is calculated on the basis of a reference value of electric capacitance which has been measured between the reference pattern and the grounded pattern. The measured value for the wiring path is compared to the calculated value to determine whether the three-dimensional wiring path is good or bad. As the multilayer wiring section has the reference patterns, the electric capacitance for the normal wiring path can be obtained by calculation without preparing the normal acceptable product.

Abstract translation: 多层布线基板具有形成有多层布线部的陶瓷基板。 其中一个导体层具有接地图案。 每个导体层具有参考图案，其可用作电容计算中的标准。 在接地图案和三维布线路径之间测量电容。 另一方面，基于在参考图案和接地图案之间测量的电容的基准值来计算理论电容。 将接线路径的测量值与计算值进行比较，以确定三维布线路径是好还是坏。 由于多层布线部分具有参考图案，所以通常在不准备正常的可接受产品的情况下通过计算获得正常布线路径的电容。

公开(公告)号：US07656166B2

公开(公告)日：2010-02-02

申请号：US12072703

申请日：2008-02-27

Applicant: Yoshiyuki Fukami

Inventor： Yoshiyuki Fukami

IPC: G01R31/02 ,  G01R27/26

CPC classification number: H05K1/0268 ,  G01R31/2805 ,  G01R31/2812 ,  H05K1/0306 ,  H05K3/4605 ,  H05K2201/09481 ,  H05K2201/09845

Abstract: A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. The ceramic substrate has an internal conductor layer, which is connected to a test pad. The first conductor layer is formed, and then an electric capacitance is measured between the test pad and a wiring pattern of the first conductor layer. On the other hand, an electrical capacitance is calculated under the normal wiring pattern condition. The measured value is compared to the calculated value to determine whether the wiring pattern is good or bad. Similar measurements and comparisons are carried out for each of the second through fifth conductor layers to determine whether a three-dimensional wiring path is good or bad. As the ceramic substrate has an internal conductor layer, the electric capacitance of the wiring can be measured without an overall grounded layer in the multilayer wiring section, which is a characteristic part different from others among a variety of the multilayer wiring boards.

Abstract translation: 多层布线基板具有形成有多层布线部的陶瓷基板。 陶瓷基板具有连接到测试垫的内部导体层。 形成第一导体层，然后在测试焊盘和第一导体层的布线图案之间测量电容。 另一方面，在正常布线图案条件下计算电容。 将测量值与计算值进行比较，以确定布线图案是好还是坏。 对于第二至第五导体层中的每一个执行类似的测量和比较，以确定三维布线路径是好还是坏。 由于陶瓷基板具有内部导体层，所以可以在多层布线部中没有整体接地层来测量布线的电容，这是各种多层布线板中与其他布线板不同的特征部分。

公开(公告)号：US20090219668A1

公开(公告)日：2009-09-03

申请号：US12392272

申请日：2009-02-25

Applicant: Chien-Min Hsu ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Huey-Ru Chang ,  Ray-Fong Hong

Inventor： Chien-Min Hsu ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Huey-Ru Chang ,  Ray-Fong Hong

IPC: H01G4/005

CPC classification number: H05K1/162 ,  H01G4/228 ,  H01G4/248 ,  H01G4/33 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/112 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2201/10674

Abstract: A capacitive device is provided. The capacitive device includes a first electrode and a second electrode below the first electrode and spaced apart from the first electrode, wherein at least one of the first electrode and the second electrode includes a plurality of conductive step sections, the plurality of conductive step sections having different heights. The capacitive device also includes an insulating region between the first electrode and the second electrode; and at least one slot formed on one of the first electrode and the second electrode.

Abstract translation: 提供了一种电容器件。 该电容性装置包括第一电极和第一电极之下并与第一电极间隔开的第二电极，其中第一电极和第二电极中的至少一个包括多个导电步骤部分，所述多个导电步骤部分具有 不同的高度 电容性装置还包括在第一电极和第二电极之间的绝缘区域; 以及形成在第一电极和第二电极之一上的至少一个槽。

公开(公告)号：US20090194322A1

公开(公告)日：2009-08-06

申请号：US12364096

申请日：2009-02-02

Applicant: Ryosuke USUI ,  Takeshi Nakamura ,  Tomohiro Kuzuu ,  Yusuke Igarashi

Inventor： Ryosuke USUI ,  Takeshi Nakamura ,  Tomohiro Kuzuu ,  Yusuke Igarashi

IPC: H05K1/16 ,  B05D3/06 ,  H05K1/11

CPC classification number: H05K1/115 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H05K1/114 ,  H05K3/0032 ,  H05K3/427 ,  H05K2201/09563 ,  H05K2201/09845 ,  H05K2203/0554 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A device mounting board has a double-layer wiring structure where a first wiring layer and a second wiring layer are stacked together with an insulating layer held between the first and second wiring layers. The first wiring layer and the second wiring layer are electrically connected by way of a via conductor provided on a side wall of a through-hole that penetrates the insulating layer. The through-hole that penetrates the insulating layer has a stepped portion. The via conductor, provided along the insulating layer in the via conductor, has a step associated with the stepped portion of the via conductor.

Abstract translation: 装置安装板具有双层布线结构，其中第一布线层和第二布线层与保持在第一和第二布线层之间的绝缘层堆叠在一起。 第一布线层和第二布线层通过设置在穿透绝缘层的通孔的侧壁上的通孔导体电连接。 穿透绝缘层的通孔具有阶梯部。 通孔导体沿着通孔导体中的绝缘层设置，具有与通孔导体的台阶部分相关联的台阶。

公开(公告)号：US20090176406A1

公开(公告)日：2009-07-09

申请号：US12328752

申请日：2008-12-04

Applicant: Roya Yaghmai ,  Frank B. Parrish ,  Daniel DeLessert

Inventor： Roya Yaghmai ,  Frank B. Parrish ,  Daniel DeLessert

IPC: H01R9/05 ,  G01R31/02

CPC classification number: H05K1/0243 ,  G01R31/2889 ,  H05K3/3405 ,  H05K2201/09618 ,  H05K2201/09809 ,  H05K2201/09845 ,  H05K2201/10356 ,  H05K2201/10446 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: In one embodiment, an interface module is provided for connecting a plurality of signal paths to a high signal density interface. The interface module includes a board having axial conductor receptacles. The axial conductor receptacles have at least one ground via extending through the board to an interface side of the board and a shield receiving hole in the board extending into the board from a cable side of the board. At least a portion of the at least one ground via being exposed within the shield receiving hole, the shield receiving hole having a plating therein contacting the portion of the at least one ground via exposed within the shield receiving hole. The axial conductor receptacles have a plated center conductor receiving hole in the board, which extends to a signal via. The signal via extends from the center conductor hole to the interface side of the board. A non-plated hole in the board is located between the plated center conductor hole and the shield receiving hole.

Abstract translation: 在一个实施例中，提供了用于将多个信号路径连接到高信号密度接口的接口模块。 接口模块包括具有轴向导体插座的板。 轴向导体插座具有通过板延伸到板的接口侧的至少一个接地，并且板中的屏蔽接收孔从板的电缆侧延伸到板中。 所述至少一个接地通孔的至少一部分被暴露在所述屏蔽接收孔内，所述屏蔽接收孔具有通过暴露在所述屏蔽接收孔内而与所述至少一个接地部分接触的电镀。 轴向导体插座在板上具有电镀中心导体接收孔，延伸到信号通孔。 信号通孔从中心导体孔延伸到电路板的接口侧。 板上的非电镀孔位于电镀中心导体孔和屏蔽接收孔之间。