公开(公告)号：US06923057B2

公开(公告)日：2005-08-02

申请号：US10791286

申请日：2004-03-03

Applicant: Daniel Sabatino

Inventor： Daniel Sabatino

IPC: G01F23/24 ,  G01F23/74 ,  H05K1/18 ,  H05K3/28 ,  G01F23/36 ,  G01F23/52 ,  G01F23/60

CPC classification number: G01F23/74 ,  G01F23/242 ,  H05K1/189 ,  H05K3/284 ,  H05K2201/10022 ,  H05K2201/10053 ,  H05K2201/10151 ,  H05K2201/10522 ,  H05K2201/10545 ,  Y10T29/49826

Abstract: A flexible liquid level sensor board assembly for application with liquid level sending units is presented. The liquid level sending unit includes a stem, float, and a flexible sensor board assembly. The flexible sensor board assembly is a distinct component of the sending unit and as such is capable of repeated insertion and removal from the stem. The flexible sensor board assembly is therefore ideal for existing/retrofit applications and new installations alike.

Abstract translation: 提出了一种用于液位发送单元的柔性液位传感器板组件。 液位发送单元包括杆，浮子和柔性传感器板组件。 柔性传感器板组件是发送单元的不同部件，因此能够从杆重复插入和移除。 因此，灵活的传感器板组件对于现有/改造应用和新的安装是理想的。

公开(公告)号：US20050109534A1

公开(公告)日：2005-05-26

申请号：US10717839

申请日：2003-11-20

Applicant: Suresh Chengalva ,  David Ihms ,  Bruce Myers

Inventor： Suresh Chengalva ,  David Ihms ,  Bruce Myers

IPC: H05K1/02 ,  H05K3/00 ,  H05K1/18

CPC classification number: H05K1/0206 ,  H01L2224/16225 ,  H01L2224/73204 ,  H05K1/0271 ,  H05K3/0061 ,  H05K2201/068 ,  H05K2201/10204 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2201/2009

Abstract: A circuit board assembly comprising a laminate substrate and a surface mount device having a CTE less than that of the laminate substrate and attached with at least one solder joint to a first surface of the laminate substrate. The assembly further includes a localized stiffener attached to a second surface of the laminate substrate so as to be directly opposite the circuit device. The localized stiffener is formed of a material and is shaped so that, when attached to the laminate substrate, the stiffener is capable of increasing the thermal cycle fatigue life of the one or more solder joints that attach the device to the substrate.

Abstract translation: 一种电路板组件，包括层压基板和表面安装装置，所述表面安装装置的CTE小于层压基板的CTE，并且与至少一个焊接接头连接到层叠基板的第一表面。 组件还包括附着到层叠基板的第二表面以便与电路装置直接相对的局部加强件。 局部加强件由材料形成并且被成形为使得当附接到层叠基板时，加强件能够增加将该装置附接到基板的一个或多个焊点的热循环疲劳寿命。

公开(公告)号：US06882536B2

公开(公告)日：2005-04-19

申请号：US10131476

申请日：2002-04-25

Applicant: Jeffrey L. Deeney ,  Joseph D. Dutson ,  Glenn C. Simon

Inventor： Jeffrey L. Deeney ,  Joseph D. Dutson ,  Glenn C. Simon

IPC: H05K7/20 ,  H01L23/36 ,  H01L23/433 ,  H05K1/02

CPC classification number: H01L23/433 ,  H01L23/36 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K2201/066 ,  H05K2201/10386 ,  H05K2201/10446 ,  H05K2201/10545 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A wrap-around cooling arrangement for a printed circuit board is disclosed. Such an arrangement comprises: a printed circuit board (“PCB”) having a first side and a second side opposite to said first side; a heat sink arranged on said first side of said PCB; a first to-be-cooled component coupled to said second side of said PCB; and a thermal jumper to thermally couple said first component on said second side to said heat sink on said first side, said jumper being configured to extend physically around a side edge of said PCB.

Abstract translation: 公开了一种用于印刷电路板的环绕冷却装置。 这种布置包括：具有第一侧和与所述第一侧相对的第二侧的印刷电路板（“PCB”）; 布置在所述PCB的所述第一侧上的散热器; 耦合到所述PCB的所述第二侧的第一被冷却部件; 以及用于将所述第二侧上的所述第一部件热耦合到所述第一侧上的所述散热器的热跳线，所述跳线构造成物理地围绕所述PCB的侧边缘延伸。

公开(公告)号：US20050007807A1

公开(公告)日：2005-01-13

申请号：US10910980

申请日：2004-08-03

Applicant: Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

Inventor： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

IPC: G11C5/00 ,  H05K1/18 ,  G11C7/00

CPC classification number: H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

Abstract: The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

公开(公告)号：US06838775B2

公开(公告)日：2005-01-04

申请号：US10693132

申请日：2003-10-23

Applicant: Makoto Takahashi

Inventor： Makoto Takahashi

IPC: H01L27/04 ,  H01L21/822 ,  H01L23/498 ,  H01L23/60 ,  H01L23/62 ,  H01L23/64 ,  H05K1/02 ,  H05K1/18 ,  H05K3/46 ,  H01L23/34

CPC classification number: H01L23/60 ,  H01L23/49822 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19106 ,  H05K1/0259 ,  H05K1/184 ,  H05K3/4602 ,  H05K2201/10545 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/0401

Abstract: The semiconductor device includes an input/output circuit, a functional module, an electrostatic discharge protection circuit and bumps. The input/output circuit is formed close to an edge of the semiconductor chip. The functional module is formed on the semiconductor chip located on a central side with regard to the input/output circuit. The electrostatic discharge protection circuit is formed in the functional module of the semiconductor chip and serves to protect a circuit located in a downstream thereof, from being destructed by electrostatic discharge. The bumps are arranged on one of major surfaces of the semiconductor chip located close to the functional module, and they are connected to the functional module via the electrostatic discharge protection circuit.

公开(公告)号：US20040250229A1

公开(公告)日：2004-12-09

申请号：US10749501

申请日：2003-12-31

Inventor： Thanh T. Tran

IPC: G06F009/45 ,  G06F017/50

CPC classification number: G06F17/5036 ,  H01L2224/16227 ,  H01L2924/15313 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/185 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: An embodiment of the present invention includes a method of providing a non-uniform distribution of decoupling capacitors to provide a more uniform noise level across the chip. Leads on a packaged semiconductor chip are grouped into two or more regions. Types of leads needing decoupling capacitors are grouped into lead categories. For each region, there may be one or more lead categories therein. One or more decoupling capacitors are preferably assigned to each lead category in each region. Calculations may be performed to estimate a desired capacitance for each decoupling capacitor for each lead category in each region. When a chip has different components operating at different switching frequencies, different voltages, and/or different switching currents, the distribution of the decoupling capacitors will likely be non-uniform to provide a more uniform noise level across the chip, as compared to a uniform distribution of decoupling capacitors for the chip.

Abstract translation: 本发明的实施例包括提供去耦电容器的不均匀分布以在芯片上提供更均匀的噪声电平的方法。 封装的半导体芯片上的引线被分组为两个或更多个区域。 需要去耦电容器的引线类型分为引线类别。 对于每个区域，其中可以有一个或多个引线类别。 一个或多个去耦电容器优选地分配给每个区域中的每个引线类别。 可以执行计算，以估计每个区域中每个引线类别的每个去耦电容器的期望电容。 当芯片具有以不同开关频率，不同电压和/或不同开关电流工作的不同部件时，去耦电容器的分布可能不均匀，以便在整个芯片上提供更均匀的噪声电平，与均匀 芯片去耦电容的分布。

公开(公告)号：US20040238932A1

公开(公告)日：2004-12-02

申请号：US10775070

申请日：2004-02-11

Inventor： Chang-Yong Park ,  Byung-Man Kim ,  Jong-Soo Choi ,  Kwang-Ho Chun ,  Se-Hyung Ryu

IPC: H01L023/02

CPC classification number: H05K1/181 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/3415 ,  H05K2201/097 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

Abstract: The array printed circuit board includes at least one circuit board having a first surface. A first layout of first and second chip mounting regions is formed on a first half of the first surface and a second layout of first, and second chip mounting regions is formed on a second half of the first surface. The first and second layouts have opposite first and second chip mounting region patterns.

Abstract translation: 阵列印刷电路板包括具有第一表面的至少一个电路板。 第一和第二芯片安装区域的第一布局形成在第一表面的第一半部分上，第一和第二芯片安装区域的第二布局形成在第一表面的第二半部分上。 第一和第二布局具有相反的第一和第二芯片安装区域图案。

公开(公告)号：US20040184248A1

公开(公告)日：2004-09-23

申请号：US10394841

申请日：2003-03-21

Applicant: Intel Corporation

Inventor： William Alger ,  Gary Long ,  Gary Brist ,  Carlos Mejia

IPC: H05K007/02

CPC classification number: H05K1/141 ,  H01L2224/73253 ,  H01L2924/15192 ,  H05K1/0263 ,  H05K3/222 ,  H05K3/3447 ,  H05K2201/10303 ,  H05K2201/10545 ,  H05K2201/10734

Abstract: An apparatus and system, as well as fabrication methods therefor, may include a conductor attached to a carrier to bridge a contact field defined by a circuit that can be mounted to a circuit board.

Abstract translation: 装置和系统及其制造方法可以包括附接到载体的导体，以桥接由可以安装到电路板的电路限定的接触场。

公开(公告)号：US20030198033A1

公开(公告)日：2003-10-23

申请号：US10383028

申请日：2003-02-25

Inventor： Augusto P. Panella ,  John E. Lopata ,  James L. McGrath ,  Arindum Dutta

IPC: H05K007/10 ,  H05K007/06

CPC classification number: H05K1/0262 ,  H05K1/141 ,  H05K2201/10189 ,  H05K2201/10325 ,  H05K2201/10545 ,  H05K2201/10704 ,  H05K2201/10719 ,  H05K2201/10734

Abstract: A processor mounted to a circuit board is provided with regulated voltage through lower-inductance circuit board traces by mounting a voltage regulator module for the processor, on the side of the circuit opposite to the processor. Current from the voltage regulator is provided to the processor by way of one or more conductors between the regulator and processor that extend through the circuit board from one side to the other. Inductance attributable to lead length is reduced by locating the voltage regulator close to its load. Circuit board space on the processor side of the circuit board is increased by moving the voltage regulator to the opposite side.

Abstract translation: 安装到电路板的处理器通过在处理器的与电路板相对的一侧安装用于处理器的电压调节器模块，通过低电感电路板迹线提供调节电压。 来自稳压器的电流通过调节器和处理器之间的一个或多个导体从一侧延伸到另一侧而提供给处理器。 通过将电压调节器放置在靠近负载的位置，减少了引脚长度的电感。 通过将电压调节器移动到相对侧，可以增加电路板处理器侧的电路板空间。

公开(公告)号：US20030110452A1

公开(公告)日：2003-06-12

申请号：US10013641

申请日：2001-12-07

Inventor： Anne Leahy ,  Ajit Sathe

IPC: G06F017/50

CPC classification number: H05K3/303 ,  H01L23/5385 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2201/2036 ,  Y02P70/613 ,  Y10T428/12396

Abstract: An electronic package with improved power delivery performance, lowering the impedance associated with the power delivery. The electronic package includes an integrated circuit die mounted on the substrate of the electronic package and decoupling capacitors placed underneath the substrate. The package further includes stand-offs placed underneath the substrate, sized for maintaining a distance between the capacitors and another substrate.

Abstract translation: 电子封装具有改进的电力传输性能，降低与电力传输相关的阻抗。 电子封装包括安装在电子封装的基板上的集成电路管芯和放置在衬底下方的去耦电容器。 封装还包括放置在基板下方的支架，其尺寸用于保持电容器和另一基板之间的距离。