公开(公告)号：US20190214357A1

公开(公告)日：2019-07-11

申请号：US15952807

申请日：2018-04-13

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chun-Te Lee ,  Ming-Sheng Liu

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/11005 ,  H01L2224/1181 ,  H01L2224/11831 ,  H01L2224/13006 ,  H01L2224/13144

Abstract: A method for manufacturing a semiconductor device includes an extra etching process. A bump or a UBM layer is etched additionally in the extra etching process after forming the semiconductor device such that the semiconductor device can conform to the standard of performance and appearance.

公开(公告)号：US10327334B1

公开(公告)日：2019-06-18

申请号：US16038436

申请日：2018-07-18

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh

IPC: H05K1/00 ,  H05K1/11 ,  H05K1/18

Abstract: A layout structure of flexible circuit board includes a flexible substrate and leads formed on a surface of the flexible substrate. Each of the leads has a bump connection end and a curved part. The bump connection end of each of the leads is located on a chip disposition area of the surface and electrically connected to a chip. The curved part has a first connection point and a second connection point, and the length of the curved part is longer than a straight-line distance between the first and second connection points.

公开(公告)号：US20160318756A1

公开(公告)日：2016-11-03

申请号：US14736328

申请日：2015-06-11

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Shu-Chen Lin ,  Fu-Yen Ho ,  Yen-Ting Chen

IPC: B81C1/00

CPC classification number: H01L23/10 ,  B81C1/00269 ,  B81C2203/019 ,  H01L21/50

Abstract: A process for manufacturing a semiconductor package having a hollow chamber includes providing a bottom substrate having a bottom plate, a ring wall and a slot, wherein the ring wall and the bottom plate form the slot; forming an under ball metallurgy layer on a surface of the ring wall;bumping a plurality of solder balls on a surface of the under ball metallurgy layer, each of the solder balls comprises a diameter, wherein a spacing is spaced apart between two adjacent solder balls; performing reflow soldering to the solder balls for making the solder balls melting and interconnecting to form a connection layer; connecting a top substrate to the bottom substrate, wherein the lot of the bottom substrate is sealed by the top substrate to form a hollow chamber used for accommodating an electronic device.

Abstract translation: 在球形冶金层的表面上碰撞多个焊球，每个焊球包括直径，其中间隔在两个相邻的焊球之间间隔开; 对所述焊球进行回流焊接，以使所述焊球熔化并互连以形成连接层; 将顶部基板连接到底部基板，其中底部基板的批次被顶部基板密封以形成用于容纳电子设备的中空室。

公开(公告)号：US20150359085A1

公开(公告)日：2015-12-10

申请号：US14317254

申请日：2014-06-27

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yi-Wen Chen ,  Yin-Chen Lin ,  Ming-Hsiao Ke ,  Yu-Chen Ma

IPC: H05K1/02

CPC classification number: H05K1/0269 ,  H05K1/0274 ,  H05K1/028 ,  H05K1/0298 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/09936

Abstract: A flexible substrate includes a base layer, a metallic layer, a solder mask layer and an identifying code, the metallic layer is disposed at a first surface of the base layer, the metallic layer comprises a plurality of traces and at least one bottom block used for defining marked position, wherein the traces and the at least one bottom block are covered with the solder mask layer, wherein above the perpendicular direction of the at least one bottom block of the metallic layer, a pre-marked area is defined on an exposing surface of the solder mask layer and by an outlined edge of the at least one bottom block, and the identifying code is formed within the pre-marked area of the solder mask layer.

Abstract translation: 柔性基板包括基底层，金属层，焊接掩模层和识别代码，金属层设置在基底层的第一表面，金属层包括多个迹线和至少一个使用的底部块 用于限定标记位置，其中所述迹线和所述至少一个底部块被所述焊接掩模层覆盖，其中在所述金属层的所述至少一个底部块的垂直方向上方，预先标记的区域被限定在曝光 焊料掩模层的表面和至少一个底部块的轮廓边缘，并且识别代码形成在焊料掩模层的预先标记的区域内。

公开(公告)号：US09177830B1

公开(公告)日：2015-11-03

申请号：US14529246

申请日：2014-10-31

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Fei-Jain Wu ,  Tsang-Sheng Liao ,  Ching-Yi Huang ,  Chun-Te Lee

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/03912 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11848 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16237 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/35 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/206

Abstract: A manufacturing method of a substrate with a bump structure, a copper layer is formed on a semiconductor substrate, and a nickel layer is formed on the copper layer. A bump structure is composed of the copper layer and the nickel layer, wherein the hardness of the bump structure after annealing process depends on the thickness of the nickel layer to meet the user's demand. The hardness of the bump structure meets the user's demand prevents a glass substrate from cracking when the substrate with the bump structure is bonded with the glass substrate.

Abstract translation: 具有凸块结构的基板的制造方法，在半导体基板上形成铜层，在铜层上形成镍层。 凸点结构由铜层和镍层组成，其中退火处理后的凸块结构的硬度取决于镍层的厚度以满足用户的需求。 凸块结构的硬度满足用户的要求，当具有凸块结构的基板与玻璃基板结合时，防止玻璃基板破裂。

公开(公告)号：US20150091141A1

公开(公告)日：2015-04-02

申请号：US14048078

申请日：2013-10-08

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Ming-Sheng Liu ,  Chih-Ping Wang

IPC: H01L23/00 ,  H01L29/02

CPC classification number: H01L23/562 ,  H01L23/31 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. The second protective layer reveals the first anti-stress zone and comprises a second surface, a first lateral side, a second lateral side and a first connection side. The second surface comprises a second anti-stress zone. An extension line of the first lateral side intersects with an extension line of the second lateral side to form a first intersection point. A zone formed by connecting the first intersection point and two points of the first connection side is the first anti-stress zone. The third protective layer reveals the second anti-stress zone and comprises a second connection side projected on the first surface to form a projection line parallel to the first connection side.

Abstract translation: 半导体结构包括载体，第一保护层，第二保护层和第三保护层。 第一保护层的第一表面包括第一抗应力区。 第二保护层揭示第一抗应力区，并包括第二表面，第一横向侧，第二横向侧和第一连接侧。 第二表面包括第二抗应力区。 第一侧面的延伸线与第二侧面的延伸线相交形成第一交点。 通过连接第一交点和第一连接侧的两个点形成的区域是第一抗应力区域。 第三保护层显示第二抗应力区域，并且包括突出在第一表面上的第二连接侧，以形成平行于第一连接侧的突出线。

公开(公告)号：US08772644B2

公开(公告)日：2014-07-08

申请号：US13644709

申请日：2012-10-04

Applicant: Chipbond Technology Corporation

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  You-Ming Hsu

IPC: H05K1/16

CPC classification number: H01L23/5223 ,  H01G4/01 ,  H01L28/86 ,  H01L2924/0002 ,  H05K1/162 ,  H01L2924/00

Abstract: A carrier with three-dimensional capacitor includes a substrate and a three-dimensional capacitor, wherein the substrate comprises a trace layer having a first terminal and a second terminal. The three-dimensional capacitor is integrally formed as one piece with the trace layer. The three-dimensional capacitor and the trace layer are made of same material. The three-dimensional capacitor comprises a first capacitance portion and a second capacitance portion, the first capacitance portion comprises a first section, a second section and a first passage, the second capacitance portion is formed at the first passage. The second capacitance portion comprises a third section, a fourth section and a second passage communicated with the first passage. The first capacitance portion is located at the second passage, a first end of the first capacitance portion connects to the first terminal, and a third end of the second capacitance portion connects to the second terminal.

Abstract translation: 具有三维电容器的载体包括基板和三维电容器，其中所述基板包括具有第一端子和第二端子的迹线层。 三维电容器与轨迹层一体形成。 三维电容器和迹线层由相同的材料制成。 三维电容器包括第一电容部分和第二电容部分，第一电容部分包括第一部分，第二部分和第一通道，第二电容部分形成在第一通道处。 第二电容部分包括与第一通道连通的第三部分，第四部分和第二通道。 第一电容部分位于第二通道处，第一电容部分的第一端连接到第一端子，第二电容部分的第三端连接到第二端子。

公开(公告)号：US20140159234A1

公开(公告)日：2014-06-12

申请号：US13743450

申请日：2013-01-17

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Kai-Yi Wang

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/48 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/014

Abstract: A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion.

Abstract translation: 半导体制造方法包括以下步骤：提供具有至少一个连接焊盘和保护层的硅衬底，形成具有至少一个第一部分和至少一个第二部分的第一种子层，形成第一光致抗蚀剂层，形成第 第一缓冲层，具有耦合部分和包层部分，去除第一光致抗蚀剂层，去除第一种子层的第二部分以形成第一凸块下金属层，在保护层和第一缓冲层上形成支撑层， 所述第一凸块下金属层具有第一环壁，所述第一缓冲层具有第二环壁，所述第一环壁，所述第二环壁和所述包层部由所述支撑层包覆，并且形成连接部和覆盖层 与连接部分的联接部分。

公开(公告)号：US20130256882A1

公开(公告)日：2013-10-03

申请号：US13903447

申请日：2013-05-28

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Shu-Chen Lin ,  Cheng-Fan Lin ,  Hua-An Dai

IPC: H01L23/58 ,  H01L23/498

CPC classification number: H01L23/58 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05099 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11906 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05599 ,  H01L2224/05552

Abstract: A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer.

公开(公告)号：US20130252374A1

公开(公告)日：2013-09-26

申请号：US13893620

申请日：2013-05-14

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Shu-Chen Lin ,  Cheng-Fan Lin ,  Yung-Wei Hsieh ,  Bo-Shiun Jiang

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances.

Abstract translation: 半导体封装方法包括提供具有多个焊盘的衬底，每个焊盘包括具有多个第一导电接触区域和多个第一非导电接触区域的第一耦合表面; 在基板上形成具有抗解离功能的导电凝胶，所述可导电凝胶包括多个导电颗粒和多个抗分解物质; 将芯片安装在基板上，所述芯片包括多个含铜凸块，每个含铜凸块包括环表面和具有多个第二导电接触区域和多个第二非导电性接触区域的第二耦合表面 接触区域，其中所述导电颗粒与所述第一导电接触区域和所述第二导电接触区域电连接，所述抗分解物质与所述第二非导电接触区域接触，并且所述环形表面被所述反 - 解离物质