公开(公告)号：US08737087B2

公开(公告)日：2014-05-27

申请号：US13729870

申请日：2012-12-28

Applicant: Ibiden Co., Ltd.

Inventor： Yasuhiro Watanabe ,  Michimasa Takahashi ,  Masakazu Aoyama ,  Takenobu Nakamura ,  Hiroyuki Yanagisawa

IPC: H05K7/10

CPC classification number: H05K1/113 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/114 ,  H05K3/243 ,  H05K3/28 ,  H05K3/282 ,  H05K3/4614 ,  H05K2201/0391 ,  H05K2201/10674 ,  H05K2203/0574 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49204 ,  H01L2224/0401

Abstract: This invention provides a multilayer printed wiring board in which electric connectivity and functionality are obtained by improving reliability and particularly, reliability to the drop test can be improved. No corrosion resistant layer is formed on a solder pad 60B on which a component is to be mounted so as to obtain flexibility. Thus, if an impact is received from outside when a related product is dropped, the impact can be buffered so as to protect any mounted component from being removed. On the other hand, land 60A in which the corrosion resistant layer is formed is unlikely to occur contact failure even if a carbon pillar constituting an operation key makes repeated contacts.

Abstract translation: 本发明提供了一种通过提高可靠性而获得电连接性和功能性的多层印刷线路板，特别是可提高落下试验的可靠性。 在要安装部件的焊料垫60B上没有形成耐腐蚀层，以获得柔性。 因此，如果在相关产品掉线时从外部接收到冲击，则可以缓冲影响，以保护所安装的组件不被移除。 另一方面，即使构成操作键的碳柱重复接触，也可能不形成耐腐蚀层的焊盘60A不会发生接触故障。

公开(公告)号：US20140139310A1

公开(公告)日：2014-05-22

申请号：US14129148

申请日：2012-06-21

Applicant: Hiroaki Asano ,  Yasuhiro Koike ,  Kiminori Ozaki ,  Hitoshi Shimadu ,  Tetsuya Furuta ,  Masao Miyake ,  Takahiro Hayakawa ,  Tomoaki Asai ,  Ryou Yamauchi

Inventor： Hiroaki Asano ,  Yasuhiro Koike ,  Kiminori Ozaki ,  Hitoshi Shimadu ,  Tetsuya Furuta ,  Masao Miyake ,  Takahiro Hayakawa ,  Tomoaki Asai ,  Ryou Yamauchi

IPC: H05K1/11 ,  H01F27/28 ,  H05K1/02

CPC classification number: H05K1/115 ,  H01F27/2804 ,  H05K1/0265 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/118 ,  H05K1/165 ,  H05K3/20 ,  H05K2201/0305 ,  H05K2201/0391 ,  H05K2201/09036 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/09745

Abstract: This wiring board is provided with an insulating core substrate, a first conductor pattern, a second conductor pattern, and a conductive material. The first conductor pattern and the second conductor pattern are adhered to the insulating core substrate. The second conductor pattern has a first surface and a second surface. The second conductor pattern has a concavity and a through-hole. The opening of the concavity that opens to the first surface and the opening of the through hole that opens to the first surface are interconnected to each other. The first conductor pattern is positioned at the opening of the concavity. The first conductor pattern and the second conductor pattern are electrically connected by means of the conductive material, which fills from the opening of the through hole that opens to the second surface.

Abstract translation: 该布线板设置有绝缘芯基板，第一导体图案，第二导体图案和导电材料。 第一导体图案和第二导体图案粘附到绝缘芯基板。 第二导体图案具有第一表面和第二表面。 第二导体图案具有凹部和通孔。 通向第一表面的凹部的开口和通向第一表面的通孔的开口相互连接。 第一导体图案位于凹部的开口处。 第一导体图案和第二导体图案通过导电材料电连接，导电材料从通孔的开口填充到第二表面。

公开(公告)号：US08723032B2

公开(公告)日：2014-05-13

申请号：US13263629

申请日：2010-03-29

Applicant: Lorenz Berchtold

Inventor： Lorenz Berchtold

IPC: H02G3/08

CPC classification number: H05K3/202 ,  H01L21/4821 ,  H01L23/49537 ,  H01L23/49579 ,  H01L2924/0002 ,  H05K2201/0391 ,  H05K2201/10924 ,  H05K2203/049 ,  H01L2924/00

Abstract: With the present invention, conductor grids for electronic housings and a manufacturing method for such conductor grids are provided. According to the invention, the conductor grid is produced from two metal strips (130, 110, 140) welded along the joint edge (150), with only one of the two metal strips needing to have a surface suitable for the wire bonding. The amount of the conventionally used, plated starting material can be considerably reduced in this way.

Abstract translation: 通过本发明，提供了电子壳体的导体栅格和这种导体栅格的制造方法。 根据本发明，导体栅格由沿着接合边缘（150）焊接的两个金属条（130,110,140）制成，只有两个金属条中的一个需要具有适于引线接合的表面。 以这种方式可以显着减少常规使用的镀覆起始材料的量。

公开(公告)号：US20120319980A1

公开(公告)日：2012-12-20

申请号：US13581542

申请日：2010-11-02

Applicant: Gen Nagaoka ,  Yasuhiro Hida ,  Hiroki Miyazaki

Inventor： Gen Nagaoka ,  Yasuhiro Hida ,  Hiroki Miyazaki

IPC: H05K1/00 ,  G06F3/041

CPC classification number: H05K1/0269 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/0326 ,  H05K2201/0338 ,  H05K2201/0391 ,  H05K2201/09918 ,  H05K2203/166

Abstract: Provided is a circuit board in which visibility of an alignment mark is improved.In a case of manufacturing a substrate module in which a touch panel (20) and an FPC (50) are electrically connected, an alignment mark in the FPC (50) is formed by an opaque metal film, so that visibility is high. Consequently, when an alignment mark (25) in the touch panel (20) is also formed by an opaque metal film, the visibility of the alignment mark (25) also becomes high. By performing alignment using the alignment marks having high visibility, alignment between the touch panel (20) and the FPC (50) can be performed easily with high precision. As a result, the yield of the substrate module increases and modification of an alignment apparatus used for alignment becomes unnecessary, so that the manufacturing cost of the substrate module can be decreased.

Abstract translation: 提供了一种改善对准标记的可视性的电路板。 在制造触摸面板（20）和FPC（50）电连接的基板模块的情况下，FPC（50）中的对准标记由不透明的金属膜形成，使得可视性高。 因此，当触摸面板（20）中的对准标记（25）也由不透明金属膜形成时，对准标记（25）的可视性也变高。 通过使用具有高可见度的对准标记进行对准，可以以高精度容易地进行触摸面板（20）和FPC（50）之间的对准。 结果，不需要基板模块的成品率的增加和用于对准的对准装置的修改，从而可以降低基板模块的制造成本。

公开(公告)号：US20120193135A1

公开(公告)日：2012-08-02

申请号：US13446727

申请日：2012-04-13

Applicant: Moises Cases ,  Tae Hong Kim ,  Rohan U. Mandrekar ,  Nusrat I. Sherali

Inventor： Moises Cases ,  Tae Hong Kim ,  Rohan U. Mandrekar ,  Nusrat I. Sherali

IPC: H05K1/11

CPC classification number: H05K3/0094 ,  H05K1/0234 ,  H05K1/0242 ,  H05K1/0251 ,  H05K1/09 ,  H05K1/167 ,  H05K3/0047 ,  H05K3/244 ,  H05K3/429 ,  H05K2201/0391 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1057 ,  Y10T428/12528

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

Abstract translation: 描述了例如多层印刷电路板（“PCB”），以及制造和使用这种包括层压层的PCB​​的方法; 穿过层压体层的至少一个通孔，以及包含在通孔内的通孔导体，所述通孔导体包括使用部分和未使用部分，所述通孔导体包括涂覆有电导率低于 铜。

公开(公告)号：US20120068960A1

公开(公告)日：2012-03-22

申请号：US13017329

申请日：2011-01-31

Applicant: Woon Chun Kim ,  Yong Soo Oh ,  Sang Hwan Oh ,  Jong Young Lee

Inventor： Woon Chun Kim ,  Yong Soo Oh ,  Sang Hwan Oh ,  Jong Young Lee

IPC: G06F3/045 ,  H05K3/00

CPC classification number: H05K1/0216 ,  G06F3/044 ,  H05K1/162 ,  H05K2201/0108 ,  H05K2201/0326 ,  H05K2201/0329 ,  H05K2201/0391 ,  H05K2203/173

Abstract: Disclosed herein are a touch screen and a method of manufacturing the same. The touch screen includes: a transparent substrate; a transparent electrode formed on the transparent substrate and including a sensing part sensing a touch input and an extension part extending from the sensing part to an edge of the transparent substrate; a wiring electrode formed at the edge of the transparent substrate and spaced apart from the extension part of the transparent electrode; and a conductive paste formed at the edge of the transparent substrate and covering both the extension part and the wiring electrode so as to electrically connect the transparent electrode to the wiring electrode, whereby the transparent electrode is formed after the wiring electrode is formed and the wiring electrode is connected to the transparent electrode through the conductive paste, thereby preventing the transparent electrode from being damaged.

Abstract translation: 这里公开了一种触摸屏及其制造方法。 触摸屏包括：透明基板; 透明电极，形成在所述透明基板上，并且包括检测触摸输入的感测部分和从所述感测部分延伸到所述透明基板的边缘的延伸部分; 布线电极，形成在透明基板的边缘并与透明电极的延伸部分间隔开; 以及形成在透明基板的边缘处并且覆盖延伸部和布线电极的导电浆料，以将透明电极电连接到布线电极，由此在布线电极形成之后形成透明电极，并且布线 电极通过导电膏连接到透明电极，从而防止透明电极损坏。

公开(公告)号：US08039972B2

公开(公告)日：2011-10-18

申请号：US12458429

申请日：2009-07-13

Applicant: Ky-hyun Jung ,  Heui-seog Kim ,  Sang-jun Kim ,  Wha-su Sin ,  Ho-geon Song ,  Jun-young Ko

Inventor： Ky-hyun Jung ,  Heui-seog Kim ,  Sang-jun Kim ,  Wha-su Sin ,  Ho-geon Song ,  Jun-young Ko

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K3/282 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/16503 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/243 ,  H05K3/3457 ,  H05K2201/0391 ,  H05K2201/0989 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A printed circuit board and method thereof and a solder ball land and method thereof. The example printed circuit board (PCB) may include a first solder ball land having a first surface treatment portion configured for a first type of resistance and a second solder ball land having a second surface treatment portion configured for a second type of resistance. The example solder ball land may include a first surface treatment portion configured for a first type of resistance and a second surface treatment portion configured for a second type of resistance. A first example method may include first treating a first surface of a first solder ball land to increase a first type of resistance and second treating a second surface of a second solder ball land to increase a second type of resistance other than the first type of resistance. A second example method may include first treating a solder ball land to increase a first type of resistance and second treating the solder ball land to increase a second type of resistance other than the first type of resistance.

Abstract translation: 一种印刷电路板及其方法和焊球地及其方法。 示例性印刷电路板（PCB）可以包括具有构造成用于第一类型电阻的第一表面处理部分的第一焊球焊盘和具有被配置为用于第二类型电阻的第二表面处理部分的第二焊球焊盘。 示例性焊球焊盘可以包括被配置为用于第一类型电阻的第一表面处理部分和被配置用于第二类型电阻的第二表面处理部分。 第一示例性方法可以包括首先处理第一焊球焊盘的第一表面以增加第一类型的电阻，并且第二处理第二焊球焊盘的第二表面以增加除第一类型电阻之外的第二类型的电阻 。 第二示例性方法可以包括首先处理焊球焊盘以增加第一类型的电阻，并且第二次处理焊球焊盘以增加除第一类型电阻之外的第二类型的电阻。

公开(公告)号：US20110236714A1

公开(公告)日：2011-09-29

申请号：US13123127

申请日：2009-10-13

Applicant: Shigeo Ohsaka ,  Toshio Kurosawa ,  Takashi Natsume

Inventor： Shigeo Ohsaka ,  Toshio Kurosawa ,  Takashi Natsume

IPC: B32B15/01 ,  C23C14/34 ,  C23C14/14

CPC classification number: C23C14/04 ,  C23C14/044 ,  C23C14/08 ,  C23C14/165 ,  C23C14/542 ,  C23C14/562 ,  H05K1/167 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2203/0361 ,  Y10T428/12493

Abstract: A copper foil with an electric resistance film in which a film with higher electrical resistivity than the metal foil is provided on the metal foil, wherein a plurality of electric resistance films with different electric resistance is arranged in parallel on the same metal foil. With conventionally used built-in resistor elements, one resistor element is configured of one type of substance on the copper foil. Nevertheless, when actually mounting the resistor elements, the circuit design tolerance can be increased and the number of man-hours can be reduced with two resistor elements and further with a plurality of resistor elements compared to a case with one resistor element. This invention aims to provide a metal foil with a built-in resistor element comprising two or more types of resistor elements on one metal foil.

Abstract translation: 在金属箔上设置有具有电阻率高于金属箔的膜的具有电阻膜的铜箔，其中在同一金属箔上平行布置具有不同电阻的多个电阻膜。 使用传统使用的内置电阻元件，一个电阻元件由铜箔上的一种物质构成。 然而，当实际安装电阻元件时，与一个电阻器元件相比，可以增加电路设计容差并且可以使用两个电阻元件减少工作时间，并且还可以减少多个电阻元件。 本发明的目的是提供一种具有内置电阻元件的金属箔，该金属箔在一个金属箔上包括两种或多种类型的电阻元件。

公开(公告)号：US20110155428A1

公开(公告)日：2011-06-30

申请号：US12785725

申请日：2010-05-24

Applicant: Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

IPC: H05K1/02 ,  H05K1/09 ,  B05D3/06 ,  B05D3/10 ,  H05K3/00

CPC classification number: H05K3/465 ,  C23C18/1612 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1689 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/045 ,  H05K3/107 ,  H05K2201/0391 ,  H05K2201/09509 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit board includes a circuit substrate, a dielectric layer, and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit, a first intaglio pattern, and a second intaglio pattern. The patterned circuit structure includes at least a second circuit and a plurality of third circuits. The second circuit is disposed in the first intaglio pattern. The third circuits are disposed in the second intaglio pattern and the blind via. Each third circuit has a first conductive layer, a second conductive layer, and a barrier layer. The first conductive layer is located between the barrier layer and the second intaglio pattern and between the barrier layer and the blind via. The second conductive layer covers the barrier layer.

Abstract translation: 电路板包括电路基板，电介质层和图案化电路结构。 电介质层覆盖电路基板的第一表面和至少第一电路。 电介质层具有第二表面，至少从第二表面延伸到第一电路的盲孔，第一凹版图案和第二凹版图案。 图案化电路结构至少包括第二电路和多个第三电路。 第二电路设置在第一凹版图案中。 第三电路设置在第二凹版图案和盲孔中。 每个第三电路具有第一导电层，第二导电层和阻挡层。 第一导电层位于阻挡层和第二凹版图案之间以及阻挡层和盲孔之间。 第二导电层覆盖阻挡层。

公开(公告)号：US07935891B2

公开(公告)日：2011-05-03

申请号：US12068992

申请日：2008-02-14

Applicant: Takashi Shuto ,  Kenji Takano ,  Kenji Iida ,  Kenichiro Abe ,  Keiji Arai ,  Kiyotaka Seyama

Inventor： Takashi Shuto ,  Kenji Takano ,  Kenji Iida ,  Kenichiro Abe ,  Keiji Arai ,  Kiyotaka Seyama

IPC: H05K1/03

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/183 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4644 ,  H05K3/4652 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2201/068 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/0156 ,  H05K2203/016 ,  H05K2203/061 ,  H05K2203/085 ,  H05K2203/1536 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49169 ,  H01L2224/0401

Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.

Abstract translation: 本发明涉及一种制造布线板的方法，包括：堆叠层，其中布线图案用绝缘层堆叠; 以及与所述堆积层分开形成的芯基板，所述方法包括以下步骤：在板状支撑体上可分离地形成所述堆积层; 将芯基板电连接到支撑体上的堆积层的布线图案; 并且从堆积层移除支撑体，以形成其中堆积层连接到芯基板的布线板。 通过可分离地形成积层和芯基板，可以制造有效显示其特性的布线板。