公开(公告)号：US20050237076A1

公开(公告)日：2005-10-27

申请号：US11170901

申请日：2005-06-30

Applicant: Alan Wood ,  Tim Corbett

Inventor： Alan Wood ,  Tim Corbett

IPC: G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/26 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L23/13 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

CPC classification number: H01L24/80 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/0491 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2831 ,  G01R31/2855 ,  G01R31/2863 ,  G01R31/2867 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/20 ,  H01L22/22 ,  H01L23/13 ,  H01L2224/16145 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

公开(公告)号：US20050214981A1

公开(公告)日：2005-09-29

申请号：US11085287

申请日：2005-03-21

Applicant: Jun Sakano ,  Kouji Takahashi ,  Yusuke Igarashi

Inventor： Jun Sakano ,  Kouji Takahashi ,  Yusuke Igarashi

IPC: H01L23/12 ,  H01L21/44 ,  H01L21/48 ,  H01L23/31 ,  H01L25/04 ,  H01L25/18 ,  H05K1/00 ,  H05K1/18 ,  H05K3/02 ,  H05K3/06 ,  H05K3/28 ,  H05K3/30 ,  H05K3/34 ,  H05K3/42

CPC classification number: H05K1/187 ,  H01L21/4832 ,  H01L23/3107 ,  H01L24/48 ,  H01L2221/68377 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/19105 ,  H05K1/0393 ,  H05K3/06 ,  H05K3/28 ,  H05K3/284 ,  H05K3/3452 ,  H05K3/423 ,  H05K2201/0394 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/0597 ,  H05K2203/0733 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing a circuit device includes the steps of preparing a conductive foil, forming conductive patterns in convex shapes by forming an isolation trench on a surface of the conductive foil, covering the surface of the conductive foil with a resin film so as to form the resin film covering the isolation trench thicker than the resin film covering upper surfaces of the conductive patterns, exposing the upper surfaces of the conductive patterns out of the resin film by removing the resin film, electrically connecting the conductive pattern exposed out of the resin film to a circuit element, forming sealing resin to seal the circuit element, and removing a rear surface of the conductive foil until the conductive patterns are mutually isolated.

Abstract translation: 一种制造电路器件的方法包括以下步骤：制备导电箔，通过在导电箔的表面上形成隔离沟槽，形成凸形形状的导电图案，用树脂膜覆盖导电箔的表面以形成 所述树脂膜覆盖比覆盖所述导电图案的上表面的所述树脂膜厚的所述隔离沟槽，通过除去所述树脂膜将所述导电图案的上表面从所述树脂膜露出，将从所述树脂膜露出的所述导电图案电连接 形成电路元件，形成密封树脂以密封电路元件，以及去除导电箔的后表面，直到导电图案相互隔离为止。

公开(公告)号：US20050213281A1

公开(公告)日：2005-09-29

申请号：US10808489

申请日：2004-03-25

Applicant: Jiangqi He ,  Ping Sun ,  Hyunjun Kim ,  Xiang Zeng

Inventor： Jiangqi He ,  Ping Sun ,  Hyunjun Kim ,  Xiang Zeng

IPC: H01G4/228 ,  H01L23/498 ,  H01L23/50 ,  H05K1/00 ,  H05K1/03 ,  H05K1/16

CPC classification number: H01G4/228 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19103 ,  H05K1/0306 ,  H05K1/162 ,  H05K2201/0187 ,  H05K2201/0394 ,  H05K2201/09581 ,  H05K2201/10378 ,  H05K2201/10674

Abstract: Extending high k material of a second dielectric layer to surround at least one thru-via designed to provide a signal other than a power signal to a die may eliminate discrete AC coupling capacitors to reduce cost and improve performance of the package.

Abstract translation: 扩展第二电介质层的高k材料以围绕设计成向芯片提供除了功率信号之外的信号的至少一个通孔可以消除离散AC耦合电容器以降低成本并提高封装的性能。

公开(公告)号：US06949771B2

公开(公告)日：2005-09-27

申请号：US10128446

申请日：2002-04-23

Applicant: Sundar A/L Natarajan Yoganandan ,  Seong Choon Lim

Inventor： Sundar A/L Natarajan Yoganandan ,  Seong Choon Lim

IPC: H01L33/54 ,  H01L33/56 ,  H01L33/60 ,  H01L33/62 ,  H01L33/64 ,  H05K1/18 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H01L33/00

CPC classification number: H01L33/486 ,  H01L33/54 ,  H01L33/642 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/10253 ,  H01L2924/3025 ,  H05K1/183 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/42 ,  H05K2201/0394 ,  H05K2201/10106 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light source suitable for surface mounting onto a printed circuit board. The light source includes a planar substrate with a centrally positioned aperture. A light emitting diode is mounted on a metallic layer covering the bottom of the aperture, and is encapsulated by a transparent encapsulant material. The metallic layer provides a thermal path for heat generated by the light emitting diode.

Abstract translation: 适用于表面安装到印刷电路板上的光源。 光源包括具有中心定位孔的平面基板。 发光二极管安装在覆盖孔底部的金属层上，并被透明的密封材料封装。 金属层为由发光二极管产生的热量提供热路径。

公开(公告)号：US20050205516A1

公开(公告)日：2005-09-22

申请号：US11073615

申请日：2005-03-08

Applicant: Hiroshi Sugimoto ,  Tatsuya Ohtaka ,  Shigeharu Takahagi

Inventor： Hiroshi Sugimoto ,  Tatsuya Ohtaka ,  Shigeharu Takahagi

IPC: B23K26/00 ,  B23K26/38 ,  B23K101/42 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46 ,  H01B13/00

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05026 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/114 ,  H05K3/0035 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09527 ,  H01L2224/05599

Abstract: A wiring board with microstrip structure has: a first conductor layer that is provided with conductor wirings to be connected to a semiconductor chip in its external terminal (bonding pad); a second conductor layer that is provided with a conductor pattern connected through a via to a ground wiring, for supplying a power supply of ground potential to the semiconductor chip; and a third conductor layer that is provided with a power supply terminal connected through a via to a power supply wiring for supplying an operation power supply of a potential other than the ground potential to the semiconductor chip, a signal terminal connected through a via to a signal wiring for transmitting an electric signal, and a ground terminal connected through a via to the conductor pattern in the second conductor layer.

Abstract translation: 具有微带结构的布线板具有：第一导体层，其在其外部端子（接合焊盘）中设置有与半导体芯片连接的导体布线; 第二导体层，其设置有通过通孔连接到接地布线的导体图案，用于向半导体芯片提供接地电位; 以及第三导体层，其具有通过通孔连接到电源布线的电源端子，用于向半导体芯片提供除了地电位以外的电位的操作电源，通过通孔连接到 用于发送电信号的信号线路，以及通过通孔连接到第二导体层中的导体图案的接地端子。

公开(公告)号：US20050200027A1

公开(公告)日：2005-09-15

申请号：US11052181

申请日：2005-02-07

Applicant: Nishant Sinha ,  Warren Farnworth

Inventor： Nishant Sinha ,  Warren Farnworth

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H05K3/24 ,  H05K3/42 ,  H01L21/44

CPC classification number: H01L21/486 ,  H01L21/2885 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L2224/02372 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/244 ,  H05K3/422 ,  H05K3/426 ,  H05K3/427 ,  H05K2201/0394 ,  H01L2924/00

Abstract: Methods for fabricating a conductive contact (through-via) through a full thickness of a substrate such as a semiconductor wafer or interposer substrate, and semiconductor devices and systems incorporating the conductive through-via are provided. The conductive contact is fabricated by applying a metal layer onto a backside of a substrate, forming a through-hole through the substrate and the metal layer, sealing the hole in the metal layer by an electroless plating process, and filling the hole by an electroplating or an electroless plating process.

Abstract translation: 提供了通过诸如半导体晶片或插入物基板的基板的整个厚度制造导电接触（贯通孔）的方法，以及结合有导电通孔的半导体器件和系统。 通过在基板的背面上施加金属层，通过基板和金属层形成贯通孔，通过化学镀处理来密封金属层中的孔，并通过电镀填充孔来制造导电接触 或化学镀工艺。

公开(公告)号：US20050167817A1

公开(公告)日：2005-08-04

申请号：US11038629

申请日：2005-01-19

Applicant: Philip Damberg

Inventor： Philip Damberg

IPC: H01L23/538 ,  H01L25/065 ,  H05K1/14 ,  H05K1/18 ,  H05K3/32 ,  H05K3/36 ,  H01L21/44

CPC classification number: H01L23/5385 ,  H01L23/5387 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/06579 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/141 ,  H05K1/189 ,  H05K3/326 ,  H05K3/363 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/049 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention is directed to a circuit panel assembly. The assembly includes a circuit panel having a top surface and a first microelectronic element mounted on the circuit panel. The first microelectronic element includes a bottom surface overlying the top surface of the circuit panel and defining a gap therebetween. The assembly further may include an array of electrical contacts exposed on the bottom surface of the first microelectronic element. The contacts include a first set connected to the circuit panel and a second set. The assembly also includes an adaptor having a substrate including a first region and an additional region. The substrate has oppositely directed inner and outer surfaces in the first region. The adaptor further having a plurality of connection pads exposed at the inner surface in the first region. The adaptor preferably includes at least one functional element in the additional region electrically connected to at least some of the connection pads. The first region of the substrate extends at least partially in the gap between the bottom surface of the first microelectronic element and the top surface of the circuit panel with the inner surface facing upwardly toward the bottom surface of the first microelectronic element. The additional region is disposed outside of the gap wherein at least some of the electrical contacts of the second set on the first microelectronic element are connected with at least some of the connection pads.

Abstract translation: 本发明涉及电路板组件。 组件包括具有顶表面的电路板和安装在电路板上的第一微电子元件。 第一微电子元件包括覆盖在电路板的顶表面上并在其间限定间隙的底表面。 组件还可以包括暴露在第一微电子元件的底表面上的电触头阵列。 触点包括连接到电路板的第一组和第二组。 组件还包括具有包括第一区域和附加区域的衬底的适配器。 衬底在第一区域中具有相对定向的内表面和外表面。 该适配器还具有暴露在第一区域的内表面处的多个连接焊盘。 适配器优选地包括在电连接到至少一些连接焊盘的附加区域中的至少一个功能元件。 衬底的第一区域至少部分地延伸在第一微电子元件的底表面和电路板的顶表面之间的间隙中，其中内表面朝向第一微电子元件的底表面。 附加区域设置在间隙的外部，其中第一微电子元件上的第二组的至少一些电触点与至少一些连接焊盘连接。

公开(公告)号：US06916685B2

公开(公告)日：2005-07-12

申请号：US10686435

申请日：2003-10-14

Applicant: Wei-Sheng Yang ,  Chih-Liang Chu ,  Kuo-Sheng Wei

Inventor： Wei-Sheng Yang ,  Chih-Liang Chu ,  Kuo-Sheng Wei

IPC: H01L21/48 ,  H05K3/24 ,  H01L21/44

CPC classification number: H05K3/242 ,  H01L21/4846 ,  H01L2924/0002 ,  H05K3/243 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2203/0542 ,  H05K2203/1581 ,  H01L2924/00

Abstract: A method of plating a metal layer over isolated pads on a semiconductor package substrate is proposed. This substrate is formed with a plurality of conductive blind vias. The isolated pads are formed on a surface of the substrate, each having a plating line extending towards one blind via but electrically insulated from the blind via by an electrically insulating region. A conductive film covers the surface of the substrate having the isolated pads, and a photoresist layer is formed over the conductive film. The photoresist layer has openings for exposing a portion of the conductive film covering the isolated pads. The exposed portion of the conductive film is removed, to allow a metal layer to be plated on the isolated pads. Then, the photoresist layer and the remainder of the conductive film are removed, and the electrical insulation between the isolated pads and the blind vias is restored.

Abstract translation: 提出了在半导体封装基板上的隔离焊盘上镀覆金属层的方法。 该衬底形成有多个导电盲孔。 孤立的焊盘形成在衬底的表面上，每个衬底具有朝向一个盲孔通过的电镀线，但是通过电绝缘区与盲孔电绝缘。 导电膜覆盖具有隔离焊盘的衬底的表面，并且在导电膜上形成光致抗蚀剂层。 光致抗蚀剂层具有用于暴露覆盖隔离垫的导电膜的一部分的开口。 去除导电膜的暴露部分，以允许将金属层电镀在隔离的焊盘上。 然后，去除光致抗蚀剂层和导电膜的其余部分，并且恢复隔离焊盘和盲孔之间的电绝缘。

公开(公告)号：US06889433B1

公开(公告)日：2005-05-10

申请号：US10030428

申请日：2000-07-10

Applicant: Ryo Enomoto ,  Takashi Kariya ,  Hajime Sakamoto

Inventor： Ryo Enomoto ,  Takashi Kariya ,  Hajime Sakamoto

IPC: H05K3/38 ,  H05K3/40 ,  H05K3/46 ,  H01K3/10

CPC classification number: H05K3/4069 ,  H05K3/386 ,  H05K3/4614 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2203/0191 ,  H05K2203/0278 ,  H05K2203/085 ,  H05K2203/1461 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: By filling a predetermined amount of conductive paste into an opening for forming a through hole or a VH formed in a resin insulating layer of a circuit board, and pressurizing the filled conductive paste under the condition of reduced pressure, removing air bubble strapped in the conductive paste.

Abstract translation: 通过将预定量的导电浆料填充到用于形成在电路板的树脂绝缘层中的通孔或VH形成的开口中，并且在减压条件下对填充的导电糊进行加压，除去粘附在导电中的气泡 糊。

公开(公告)号：US20050040542A1

公开(公告)日：2005-02-24

申请号：US10954294

申请日：2004-10-01

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L23/12 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L24/10 ,  H01L21/486 ,  H01L21/563 ,  H01L23/13 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/3457 ,  H05K3/386 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0394 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05647 ,  H01L2224/05099 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: The semiconductor device comprises an insulating film in which penetrating holes are formed, a semiconductor chip having electrodes, a wiring pattern adhered by an adhesive over a region including penetrating holes on one side of the insulating film and electrically connected to the electrodes of the semiconductor chip, and external electrodes provided on the wiring pattern through the penetrating holes and projecting from the surface opposite to the surface of the substrate on which the wiring pattern is formed. Part of the adhesive is drawn in to be interposed between the penetrating holes and external electrodes.

Abstract translation: 半导体器件包括其中形成有穿透孔的绝缘膜，具有电极的半导体芯片，通过粘合剂粘附在包括在绝缘膜的一侧上的穿透孔的区域上的电连接到半导体芯片的电极的布线图案 以及通过贯通孔设置在布线图案上并从与形成布线图案的基板的表面相反的表面突出的外部电极。 粘合剂的一部分被拉入以插入在穿透孔和外部电极之间。