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公开(公告)号：US09386688B2
公开(公告)日：2016-07-05
申请号：US12945825
申请日：2010-11-12
Applicant: James MacDonald , William McKinzie, III , Walter Parmon , Lawrence Rubin
Inventor： James MacDonald , William McKinzie, III , Walter Parmon , Lawrence Rubin
IPC: H01Q1/52 , H05K1/02 , H01L23/552 , H01L23/66 , H01Q1/22 , H01Q1/32 , H01Q9/04 , H01Q13/18 , H01Q15/00 , H01L23/00 , H05K1/18
CPC classification number: H05K1/0236 , H01L23/552 , H01L23/66 , H01L24/13 , H01L24/16 , H01L2223/6627 , H01L2223/6677 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2924/01019 , H01L2924/14 , H01L2924/1421 , H01L2924/15311 , H01L2924/16152 , H01L2924/167 , H01Q1/2283 , H01Q1/3233 , H01Q9/0407 , H01Q13/18 , H01Q15/0086 , H05K1/095 , H05K1/116 , H05K1/165 , H05K1/167 , H05K1/181 , H05K2201/0329 , H05K2201/09072 , H05K2201/094 , H05K2201/09454 , Y10T29/49016 , H01L2924/00
Abstract: An integrated antenna package includes an interposer, an integrated circuit die, and a cap that forms a cavity within the integrated antenna package. A lossy ERG structure resides at the cap overlying the integrated circuit device. A lossless EBG structure resides at the cap overlying a microstrip feedline. A radar module includes a plurality of receive portions, each receive portion including a parabolic structure having a reflective surface, an absorber structure, a lens, and an antenna.
Abstract translation: 集成天线封装包括内插器，集成电路管芯和在集成天线封装内形成空腔的盖。 有损的ERG结构位于覆盖集成电路器件的盖子上。 无损的EBG结构位于覆盖微带馈线的帽子上。 雷达模块包括多个接收部分，每个接收部分包括具有反射表面的抛物线结构，吸收体结构，透镜和天线。
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132.发明授权公开(公告)号：US09192044B2
公开(公告)日：2015-11-17
申请号：US13862038
申请日：2013-04-12
Applicant: CANON KABUSHIKI KAISHA
Inventor： Seiji Hayashi , Takuya Kondo , Shoji Matsumoto
CPC classification number: H05K1/0216 , H01L23/49827 , H01L23/49838 , H01L2224/48227 , H05K1/0228 , H05K1/0242 , H05K1/0298 , H05K1/11 , H05K1/114 , H05K1/116 , H05K1/14 , H05K1/141 , H05K1/162 , H05K1/18 , H05K2201/0939 , H05K2201/09418 , H05K2201/09454 , H05K2201/09463 , H05K2201/09636 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734
Abstract: First and second signal wiring patterns are formed in a first conductor layer. A first electrode pad electrically connected to the first signal wiring pattern through a first via and a second electrode pad electrically connected to the second signal wiring pattern through a second via are formed in a second conductor layer as a surface layer. A third conductor layer is disposed between the first conductor layer and the second conductor layer with an insulator interposed between those conductor layers. A first pad electrically connected to the first via is formed in the third conductor layer. The first pad includes an opposed portion which overlaps the second electrode pad as viewed in a direction perpendicular to the surface of a printed board and which is opposed to the second electrode pad through intermediation of the insulator. This enables reduction of crosstalk noise caused between the signal wirings.
Abstract translation: 第一和第二信号布线图案形成在第一导体层中。 通过第一通孔电连接到第一信号布线图案的第一电极焊盘和通过第二通孔电连接到第二信号布线图案的第二电极焊盘形成在作为表面层的第二导体层中。 第三导体层设置在第一导体层和第二导体层之间，绝缘体插在这些导体层之间。 电连接到第一通孔的第一焊盘形成在第三导体层中。 第一焊盘包括与垂直于印刷电路板的表面的方向观察的与第二电极焊盘重叠并且通过绝缘体与第二电极焊盘相对的相对部分。 这使得能够减少在信号布线之间引起的串扰噪声。
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公开(公告)号：US09155196B2
公开(公告)日：2015-10-06
申请号：US14290193
申请日：2014-05-29
Applicant: IBIDEN CO., LTD.
Inventor： Haruhiko Morita
CPC classification number: H05K1/165 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/3511 , H05K1/0225 , H05K1/0366 , H05K1/116 , H05K3/244 , H05K3/4602 , H05K2201/0191 , H05K2201/0293 , H05K2201/0347 , H05K2201/0723 , H05K2201/0792 , H05K2201/09136 , H05K2201/09263 , H05K2201/09454 , H05K2201/09527 , H05K2201/096 , H05K2201/09672 , H05K2201/09836
Abstract: A wiring board includes a substrate having a laminated-inductor forming portion and including multiple first insulation layers and a second insulation layer formed on a first side of the first insulation layers such that the first insulation layers have the laminated-inductor forming portion, and a planar conductor formed on the second insulation layer of the substrate and formed to shield electromagnetic force generated from the laminated-inductor forming portion of the substrate. The laminated-inductor forming portion of the substrate has multiple inductor patterns formed on the first insulation layers and multiple via conductors connecting the inductor patterns through the first insulation layers, and the inductor patterns include an uppermost inductor pattern formed between the second insulation layer and the first insulation layers such that the uppermost inductor pattern has a distance of 100 μm or more from the planar conductor.
Abstract translation: 布线基板包括具有层叠电感器形成部分并且包括多个第一绝缘层的基板和形成在第一绝缘层的第一侧上的第二绝缘层，使得第一绝缘层具有层叠电感器形成部分，以及 形成在基板的第二绝缘层上并形成以屏蔽从基板的层叠电感器形成部分产生的电磁力的平面导体。 衬底的层叠电感器形成部分具有形成在第一绝缘层上的多个电感器图案和通过第一绝缘层连接电感器图案的多个通孔导体，并且电感器图案包括形成在第二绝缘层和 第一绝缘层，使得最上层的电感器图案与平面导体的距离为100μm以上。
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公开(公告)号：US08970327B2
公开(公告)日：2015-03-03
申请号：US13139786
申请日：2008-12-25
Applicant: Taras Kushta
Inventor： Taras Kushta
CPC classification number: H01P1/2056 , H01P1/203 , H01P7/04 , H01P7/08 , H05K1/0222 , H05K1/0251 , H05K1/116 , H05K3/429 , H05K2201/09454 , H05K2201/09618 , H05K2201/09627 , H05K2201/09718
Abstract: A filter is provided with a planar transmission line and a combined via structure connected to (both) one ends of the planar transmission line. The planar transmission line and the combined via structure are disposed in a same multilayer board. The combined via structure comprises two working parts. The first working part comprises a segment of signal via and a plurality of segments of ground vias surrounding the signal via. The second working part comprises a segment of the same signal via, a plurality of segments of the same ground vias, smooth conductive plate and corrugated conductive plate. The smooth conductive plate and the corrugated conductive plate are connected to the signal via. The second working part comprises a segment of the same signal via, a plurality of segments of the same ground vias and corrugated conductive plate. The corrugated conductive plate is connected to the signal via.
Abstract translation: 滤波器设置有平面传输线和连接到平面传输线的一端的（两者）的组合通孔结构。 平面传输线和组合通孔结构设置在相同的多层板中。 组合通孔结构包括两个工作部件。 第一工作部分包括信号通道的段和围绕信号通路的多个接地通路段。 第二工作部分包括相同信号通道的段，相同接地通孔的多个段，平滑导电板和波纹状导电板。 平滑导电板和波纹状导电板连接到信号通孔。 第二工作部分包括相同信号通道的段，相同接地通孔和波纹状导电板的多个段。 波纹状导电板与信号通孔相连。
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公开(公告)号：US20140353022A1
公开(公告)日：2014-12-04
申请号：US14290193
申请日：2014-05-29
Applicant: IBIDEN CO., LTD.
Inventor： Haruhiko MORITA
CPC classification number: H05K1/165 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/3511 , H05K1/0225 , H05K1/0366 , H05K1/116 , H05K3/244 , H05K3/4602 , H05K2201/0191 , H05K2201/0293 , H05K2201/0347 , H05K2201/0723 , H05K2201/0792 , H05K2201/09136 , H05K2201/09263 , H05K2201/09454 , H05K2201/09527 , H05K2201/096 , H05K2201/09672 , H05K2201/09836
Abstract: A wiring board includes a substrate having a laminated-inductor forming portion and including multiple first insulation layers and a second insulation layer formed on a first side of the first insulation layers such that the first insulation layers have the laminated-inductor forming portion, and a planar conductor formed on the second insulation layer of the substrate and formed to shield electromagnetic force generated from the laminated-inductor forming portion of the substrate. The laminated-inductor forming portion of the substrate has multiple inductor patterns formed on the first insulation layers and multiple via conductors connecting the inductor patterns through the first insulation layers, and the inductor patterns include an uppermost inductor pattern formed between the second insulation layer and the first insulation layers such that the uppermost inductor pattern has a distance of 100 μm or more from the planar conductor.
Abstract translation: 布线基板包括具有层叠电感器形成部分并且包括多个第一绝缘层的基板和形成在第一绝缘层的第一侧上的第二绝缘层，使得第一绝缘层具有层叠电感器形成部分，以及 形成在基板的第二绝缘层上并形成以屏蔽从基板的层叠电感器形成部分产生的电磁力的平面导体。 衬底的层叠电感器形成部分具有形成在第一绝缘层上的多个电感器图案和通过第一绝缘层连接电感器图案的多个通孔导体，并且电感器图案包括形成在第二绝缘层和 第一绝缘层，使得最上层的电感器图案与平面导体的距离为100μm以上。
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Patent Agency Ranking
136.发明授权Construction of reliable stacked via in electronic substrates—vertical stiffness control method 有权在电子基板中构建可靠的堆叠通孔 - 垂直刚度控制方法公开(公告)号：US08258410B2
公开(公告)日：2012-09-04
申请号：US12020534
申请日：2008-01-26
Applicant: Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
Inventor： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
CPC classification number: H01L23/49827 , H01L23/49838 , H01L2224/05001 , H01L2224/05548 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0271 , H05K1/116 , H05K3/4602 , H05K2201/0347 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/0969 , Y10T29/49155 , H01L2224/05599 , H01L2224/05099
Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the platted through hole landing.
Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括支撑多个堆叠的通孔的平板通孔平台。 平板通孔着陆包括顺应中心区域; 以及用于连接板状通孔底板的柔性中心区域的弹簧状刚度减小连接器。
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公开(公告)号：US08242385B2
公开(公告)日：2012-08-14
申请号：US12826276
申请日：2010-06-29
Applicant: Satoshi Kawai
Inventor： Satoshi Kawai
IPC: H05K1/11
CPC classification number: H05K1/116 , H05K1/0224 , H05K1/113 , H05K3/429 , H05K2201/062 , H05K2201/0723 , H05K2201/093 , H05K2201/09454 , H05K2201/0969 , H05K2201/09709
Abstract: An electronic circuit unit includes a multi-layer substrate in which high frequency circuits are provided on two different layers and a ground layer is formed between the two layers, and grounding lands connected to peripheral conductive members through connection bars formed on a plurality of layers of the multi-layer substrate. The grounding lands are connected to each other through a via hole and conducted to the ground layer, and the connection bars protruding radially outward from at least two grounding lands provided on different layers are arranged in different directions with respect to a circumferential direction such that the connection bars do not overlap each other along a thickness direction of the multi-layer substrate.
Abstract translation: 电子电路单元包括多层基板，其中高频电路设置在两个不同的层上，并且在两层之间形成接地层，以及通过形成在多个层上的连接条连接到外围导电构件的接地区 多层基板。 接地平台通过通孔相互连接并传导到接地层，并且从设置在不同层上的至少两个接地台径向向外突出的连接杆相对于圆周方向布置在不同的方向上，使得 连接条不沿着多层基板的厚度方向彼此重叠。
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138.发明申请公开(公告)号：US20120168220A1
公开(公告)日：2012-07-05
申请号：US13281264
申请日：2011-10-25
Applicant: Han Ul Lee , Byung Bae SEO , Chang Sup RYU , Yong Sam LEE
Inventor： Han Ul Lee , Byung Bae SEO , Chang Sup RYU , Yong Sam LEE
CPC classification number: H05K3/429 , H05K2201/09454 , H05K2201/09563 , H05K2201/096 , H05K2203/107 , H05K2203/1572 , Y10T29/49165
Abstract: Disclosed herein are a multi-layer printed circuit board and a method of manufacturing the same. In the multi-layer printed circuit board and the method of manufacturing the same, circuit layers formed in a plurality of insulating layers are electrically interconnected through vias formed in a lump, thereby making it possible to secure bonding reliability of an interlayer circuit layer and more stably secure performance of the printed circuit board. In addition, since a stacked type via structure may be implemented by performing a via hole drilling process, a desmear process, and a copper plating process only one time after an insulating layer and an circuit layer are stacked, a manufacturing process, a manufacturing time, and manufacturing costs of the stacked type via structure may be reduced.
Abstract translation: 这里公开了多层印刷电路板及其制造方法。 在多层印刷电路板及其制造方法中，形成在多个绝缘层中的电路层通过一体形成的通孔电连接，从而可以确保层间电路层的结合可靠性和更多 稳定地确保印刷电路板的性能。 此外，由于堆叠型通孔结构可以通过在绝缘层和电路层堆叠后一次进行通孔钻孔工艺，去污工艺和镀铜处理来实现，制造工艺，制造时间 ，并且可以减小层叠型通孔结构的制造成本。
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公开(公告)号：US20120119969A1
公开(公告)日：2012-05-17
申请号：US12945825
申请日：2010-11-12
Applicant: James MacDonald , William McKinzie, III , Walter Parmon , Lawrence Rubin
Inventor： James MacDonald , William McKinzie, III , Walter Parmon , Lawrence Rubin
CPC classification number: H05K1/0236 , H01L23/552 , H01L23/66 , H01L24/13 , H01L24/16 , H01L2223/6627 , H01L2223/6677 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2924/01019 , H01L2924/14 , H01L2924/1421 , H01L2924/15311 , H01L2924/16152 , H01L2924/167 , H01Q1/2283 , H01Q1/3233 , H01Q9/0407 , H01Q13/18 , H01Q15/0086 , H05K1/095 , H05K1/116 , H05K1/165 , H05K1/167 , H05K1/181 , H05K2201/0329 , H05K2201/09072 , H05K2201/094 , H05K2201/09454 , Y10T29/49016 , H01L2924/00
Abstract: An integrated antenna package includes an interposer, an integrated circuit die, and a cap that forms a cavity within the integrated antenna package. A lossy ERG structure resides at the cap overlying the integrated circuit device. A lossless EBG structure resides at the cap overlying a microstrip feedline. A radar module includes a plurality of receive portions, each receive portion including a parabolic structure having a reflective surface, an absorber structure, a lens, and an antenna.
Abstract translation: 集成天线封装包括内插器，集成电路管芯和在集成天线封装内形成空腔的盖。 有损的ERG结构位于覆盖集成电路器件的盖子上。 无损的EBG结构位于覆盖微带馈线的帽子上。 雷达模块包括多个接收部分，每个接收部分包括具有反射表面的抛物线结构，吸收体结构，透镜和天线。
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公开(公告)号：US20110290544A1
公开(公告)日：2011-12-01
申请号：US13206084
申请日：2011-08-09
Applicant: Naohiro Hirose , Takashi Kariya , Yoji Mori
Inventor： Naohiro Hirose , Takashi Kariya , Yoji Mori
IPC: H05K1/02
CPC classification number: H01R9/09 , H01L23/12 , H01L23/48 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H05K1/0256 , H05K1/0263 , H05K1/0265 , H05K1/0271 , H05K1/113 , H05K1/115 , H05K1/116 , H05K3/184 , H05K3/241 , H05K3/382 , H05K3/4602 , H05K3/4661 , H05K2201/09227 , H05K2201/09236 , H05K2201/09254 , H05K2201/09272 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/09627 , H05K2201/09727 , H05K2201/09781 , H05K2201/10734 , H05K2203/0594 , Y10T29/49155 , Y10T29/49194 , Y10T428/31504
Abstract: A printed wiring board including a core substrate, a build-up layer formed over the core substrate and including a first insulating layer, a conductor layer formed over the first insulating layer, and a second insulating layer formed over the conductor layer, and one or more wiring patterns formed over the first insulating layer. The conductor layer includes conductor portions, and the conductor portions have notched portions, respectively, facing each other across the wiring pattern.
Abstract translation: 一种印刷电路板，包括芯基板，形成在所述芯基板上并包括第一绝缘层的堆积层，形成在所述第一绝缘层上的导体层和形成在所述导体层上的第二绝缘层，以及一个或 在第一绝缘层上形成更多的布线图案。 导体层包括导体部分，并且导体部分分别具有跨越布线图案彼此面对的切口部分。
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