公开(公告)号：US07906377B2

公开(公告)日：2011-03-15

申请号：US12432367

申请日：2009-04-29

Applicant: Wen-Yuan Chang ,  Wei-Cheng Chen ,  Yeh-Chi Hsu

Inventor： Wen-Yuan Chang ,  Wei-Cheng Chen ,  Yeh-Chi Hsu

IPC: H01L21/50

CPC classification number: H05K3/242 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2203/054 ,  H05K2203/0723 ,  H01L2224/05099

Abstract: A fabrication method of a circuit board is provided. A substrate, a top pad, a base pad electrically connecting the top pad, and a top and a base solder resist layers are provided. The top and the base pads are disposed on two opposite surfaces of the substrate, respectively. The top solder resist layer having a first opening partially exposing the top pad and the base solder resist layer having a second opening partially exposing the base pad are disposed on the two surfaces, respectively. A conductive layer covering the base solder resist layer and the base pad is formed. A plating resist layer having a third opening is formed on the conductive layer. A current is applied to the conductive layer through the third opening for electroplating a pre-bump on the top pad. The plating resist layer and the conductive layer are then removed.

Abstract translation: 提供了电路板的制造方法。 提供了一种衬底，顶部焊盘，电连接顶部焊盘以及顶部和基底阻焊层的基座。 顶部和底座分别设置在基板的两个相对的表面上。 具有部分露出顶部焊盘的第一开口和具有部分暴露基板的第二开口的基底阻焊层的顶部阻焊层分别设置在两个表面上。 形成覆盖基底阻焊层和基座的导体层。 在导电层上形成具有第三开口的电镀抗蚀剂层。 通过第三开口将电流施加到导电层，用于在顶部焊盘上电镀预凸块。 然后除去电镀抗蚀剂层和导电层。

公开(公告)号：US07884463B2

公开(公告)日：2011-02-08

申请号：US12626037

申请日：2009-11-25

Applicant: Takashi Ozawa ,  Hitoshi Sato

Inventor： Takashi Ozawa ,  Hitoshi Sato

IPC: H01L23/495

CPC classification number: H05K1/114 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/113 ,  H05K2201/09627 ,  H05K2201/10674 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: On a semiconductor element loading face, wiring patterns are drawn out from those formed in the vicinity of the edge of the semiconductor element of the loading pads formed to correspond to the electrode terminals of the semiconductor element, and connected to via pads formed in the vicinity of the edge of the semiconductor element loading face; area pads constructed of the loading pads corresponding to the electrode terminals formed in the central region of the semiconductor element and its vicinity are electrically connected to external connecting terminal pads formed in the central region on the other side of the wiring board and its vicinity, through the nearest area pad vias encircled by the external connecting terminal pads and passing through the wiring board and the wiring patterns; and a plurality of the loading pads constituting the area pads commonly use one of the area pad vias.

Abstract translation: 在半导体元件装载面上，从形成在与半导体元件的电极端子对应的装载焊盘的半导体元件的边缘附近形成的布线图案被拉出，并连接到形成在其附近的通孔焊盘 的半导体元件装载面的边缘; 由与形成在半导体元件的中心区域的电极端子对应的负载焊盘构成的区域焊盘电连接到形成在布线基板的另一侧的中央区域的外部连接端子焊盘及其附近，通过 由外部连接端子焊盘包围并通过布线板和布线图案的最近的区域焊盘通孔; 并且构成区域焊盘的多个装载焊盘通常使用区域焊盘通孔中的一个。

公开(公告)号：US20110024177A1

公开(公告)日：2011-02-03

申请号：US12511161

申请日：2009-07-29

Applicant: Hung Tao Wong ,  Chung Yang Wu

Inventor： Hung Tao Wong ,  Chung Yang Wu

IPC: H05K1/11 ,  H05K3/34

CPC classification number: H05K3/3447 ,  H05K1/0201 ,  H05K1/0272 ,  H05K1/116 ,  H05K3/3468 ,  H05K3/429 ,  H05K2201/062 ,  H05K2201/09063 ,  H05K2201/09627 ,  Y10T29/49144

Abstract: A method for soldering electronic components of a circuit board and a circuit board structure thereof are presented. The method includes providing a circuit board first; disposing at least one solder hole and at least one heat collecting hole on the circuit board, in which the heat collecting hole is disposed around the solder hole to form a heat collecting area; extending a pin of an electronic component into the solder hole; filling a solder within the solder hole through a soldering process; and keeping heat of the solder in the heat collecting area by the heat collecting hole. Thus, the pin of the electronic component within the solder hole is successfully combined with the solder.

Abstract translation: 本发明提供一种焊接电路板的电子部件及其电路板结构的方法。 该方法包括首先提供电路板; 在所述电路板上设置至少一个焊料孔和至少一个集热孔，其中所述集热孔设置在所述焊料孔周围以形成集热区域; 将电子部件的销延伸到焊料孔中; 通过焊接工艺在焊料孔内填充焊料; 并且通过集热孔将焊料的热量保持在集热区域中。 因此，焊料孔内的电子部件的销被成功地与焊料组合。

公开(公告)号：US20110011636A1

公开(公告)日：2011-01-20

申请号：US12654491

申请日：2009-12-22

Applicant: Kwang Jae Oh ,  Joo Yong Kim ,  Yoon Hyuck Choi

Inventor： Kwang Jae Oh ,  Joo Yong Kim ,  Yoon Hyuck Choi

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H05K1/167 ,  H05K3/4644 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2203/171 ,  Y10T29/49082 ,  Y10T29/4913 ,  Y10T29/49162

Abstract: There are provided a multilayer wiring board and a method of manufacturing the same. The multilayer wiring board according to an aspect of the invention may include: a main body having a plurality of insulting layers stacked upon each other, including a first layer provided as an inner layer and a second layer provided as an outer layer; a first resistor provided on the first layer; and a second resistor provided on the second layer, connected in parallel with the first resistor, and having a smaller area than the first resistor. The multilayer wiring board obtains a target resistance value using the first and second resistors formed on the first and second layers. The second resistor, formed on the outer layer, can have a smaller area than the first resistor. Accordingly, the usable area of the outer layer is increased to thereby reduce the size of the multilayer wiring board.

Abstract translation: 提供了一种多层布线板及其制造方法。 根据本发明的一个方面的多层布线板可以包括：主体，其具有堆叠在一起的多个绝缘层，包括设置为内层的第一层和设置为外层的第二层; 设置在第一层上的第一电阻器; 以及设置在所述第二层上的与所述第一电阻并联连接并且具有比所述第一电阻器小的面积的第二电阻器。 多层布线基板使用形成在第一层和第二层上的第一和第二电阻来获得目标电阻值。 形成在外层上的第二电阻器可以具有比第一电阻器更小的面积。 因此，增加了外层的可用面积，从而减小了多层布线板的尺寸。

公开(公告)号：US20100258342A1

公开(公告)日：2010-10-14

申请号：US12549875

申请日：2009-08-28

Applicant: John L. Parker

Inventor： John L. Parker

IPC: H05K1/11 ,  H05K13/00

CPC classification number: A61N1/3754 ,  H01L23/10 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01079 ,  H01L2924/15184 ,  H05K1/115 ,  H05K3/4611 ,  H05K2201/09509 ,  H05K2201/09627 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A feed through for an active implantable medical device (AIMD). The feed through comprises first and second substantially planar, electrically non-conductive and fluid impermeable substrates usable for semiconductor device fabrication, each comprising: an aperture there through, and a contiguous metalized layer on the substrate surface that is co-existent with a section of the perimeter of the aperture and extends from the aperture; and a bond layer affixing the metalized layers of the first and second substrates to one another such that the apertures are not aligned with one another, and such that the metalized regions form a conductive pathway between the apertures.

Abstract translation: 用于主动植入式医疗装置（AIMD）的进料通道。 进料通道包括可用于半导体器件制造的第一和第二基本上平面的，不导电的和流体不可渗透的基底，每个基底平面的，非导电的和不透流体的基底，每个包括：通孔的孔，以及与基底表面共同存在的基底表面上的连续的金属化层 孔的周长并从孔延伸; 以及将第一和第二基板的金属化层彼此粘合使得孔不彼此对准并且使得金属化区域在孔之间形成导电路径的接合层。

公开(公告)号：US07804692B2

公开(公告)日：2010-09-28

申请号：US11614846

申请日：2006-12-21

Applicant: Huajun Lu

Inventor： Huajun Lu

IPC: H05K1/18

CPC classification number: H05K1/0231 ,  H05K1/0237 ,  H05K3/429 ,  H05K2201/09254 ,  H05K2201/09627 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y10T29/4913 ,  Y10T29/49169

Abstract: A method and system for placing multiple loads in a high-speed system are disclosed. In one embodiment, the first load and the second load are placed on the first side and the second side of the printed circuit board, respectively. In addition, the first signal pin of the first load is vertically aligned with the second signal pin of the second load with an offset; the terminating end of a trace, which is connected to a driver on the printed circuit board, the first signal pin, and the second signal pin are connected at a T-point. The printed circuit also includes the first decoupling capacitor on the second side and the second decoupling capacitor on the first side. The first decoupling capacitor is connected to the first power pin of the first load. Similarly, the second decoupling capacitor is connected to a second power pin of the second load.

Abstract translation: 公开了一种用于将多个负载放置在高速系统中的方法和系统。 在一个实施例中，第一负载和第二负载分别放置在印刷电路板的第一侧和第二侧上。 此外，第一负载的第一信号引脚与第二负载的第二信号引脚垂直对准偏移; 连接到印刷电路板上的驱动器的迹线的终止端，第一信号引脚和第二信号引脚在T点连接。 印刷电路还包括第二侧上的第一去耦电容器和第一侧上的第二去耦电容器。 第一去耦电容器连接到第一负载的第一电源引脚。 类似地，第二去耦电容器连接到第二负载的第二电源引脚。

公开(公告)号：US07797663B2

公开(公告)日：2010-09-14

申请号：US11696659

申请日：2007-04-04

Applicant: Steven C. Bird ,  Varoujan Malian ,  Mudasir Ahmad ,  Charles H. Casale ,  Danlu Tang

Inventor： Steven C. Bird ,  Varoujan Malian ,  Mudasir Ahmad ,  Charles H. Casale ,  Danlu Tang

IPC: G06F17/50

CPC classification number: G01R31/2818 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/0262 ,  H05K1/0268 ,  H05K1/113 ,  H05K1/181 ,  H05K3/3421 ,  H05K3/3457 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/0367 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/09663 ,  H05K2201/10333 ,  H05K2201/10462 ,  H05K2201/10484 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611

Abstract: Methods and apparatus for accessing a high speed signal routed on a conductive trace on an internal layer of a printed circuit board (PCB) using high density interconnect (HDI technology) are provided. The conductive trace may be coupled to a microvia (μVia) having a conductive dome disposed above the outer layer pad of the μVia. In-circuit test (ICT) fixtures or high speed test probes may interface with the conductive dome to test the high speed signal with decreased reflection loss and other parasitic effects when compared to conventional test points utilizing plated through-hole (PTH) technology.

Abstract translation: 提供了使用高密度互连（HDI技术）访问在印刷电路板（PCB）的内层上的导电迹线上路由的高速信号的方法和装置。 导电迹线可以耦合到具有设置在μVia的外层焊盘上方的导电圆顶的微孔（μVia）。 与使用电镀通孔（PTH）技术的常规测试点相比，在线测试（ICT）固定装置或高速测试探头可与导电圆顶接口以测试具有降低的反射损耗和其他寄生效应的高速信号。

公开(公告)号：US07786571B2

公开(公告)日：2010-08-31

申请号：US12136316

申请日：2008-06-10

Applicant: Pao-Hung Chou ,  Chi-Liang Chu ,  Wei-Chun Wang

Inventor： Pao-Hung Chou ,  Chi-Liang Chu ,  Wei-Chun Wang

IPC: H01L23/34

CPC classification number: H05K1/0206 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/183 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A heat-conductive package structure includes a carrier board having a first surface and an opposing second surface and formed with a through opening passing the carrier board; a first heat-conductive structure including a heat-conductive hole in the through opening, a first heat-conductive sheet on the carrier board, and a second heat-conductive sheet on the carrier board, wherein the first and second heat-conductive sheets are conductively connected by the heat-conductive hole; a first dielectric layer formed on the first surface of the carrier board and formed with a first opening for exposing the first heat-conductive sheet; a second dielectric layer formed on the second surface of the carrier board and formed with at least a second opening for exposing a portion of the second heat-conductive sheet; and a second heat-conductive structure formed in the second opening and mounted on the second heat-conductive sheet.

Abstract translation: 导热封装结构包括具有第一表面和相对的第二表面的载体板，并形成有穿过承载板的通孔; 第一导热结构，其包括在通孔中的导热孔，载体板上的第一导热片和载体板上的第二导热片，其中第一和第二导热片是 由导热孔导电连接; 第一介电层，形成在所述载板的所述第一表面上，并形成有用于暴露所述第一导热片的第一开口; 第二电介质层，形成在所述载体板的第二表面上，并形成有用于暴露所述第二导热片的一部分的至少第二开口; 以及形成在第二开口中并安装在第二导热片上的第二导热结构。

公开(公告)号：US07727004B2

公开(公告)日：2010-06-01

申请号：US11480087

申请日：2006-06-30

Applicant: David Louis Spengler ,  Bill A. Pagano

Inventor： David Louis Spengler ,  Bill A. Pagano

IPC: G01R27/02

CPC classification number: H05K1/0268 ,  H05K3/306 ,  H05K3/42 ,  H05K2201/09627 ,  H05K2201/1059 ,  H05K2203/175

Abstract: An apparatus and associated method for analyzing a communications link between two components on a common PCB. The communications link has a pair of through-board conductors connected by a first conductive etching on one side of the PCB. The communications link further has second etchings on an opposite side of the PCB respectively connecting each of the through-board conductors to one of the components. The first conductive etching can operably be open-circuited and connectors of an analyzer can be fitted to the through-board conductors to test the communications link between the components.

Abstract translation: 一种用于分析公共PCB上的两个组件之间的通信链路的装置和相关联的方法。 通信链路具有通过PCB的一侧上的第一导电蚀刻而连接的一对贯通板导体。 通信链路还在PCB的相对侧上具有第二蚀刻，其分别将每个贯通板导体连接到其中一个部件。 第一导电蚀刻可以可操作地开路，并且分析仪的连接器可以安装到贯穿板导体，以测试部件之间的通信链路。

公开(公告)号：US20100061736A1

公开(公告)日：2010-03-11

申请号：US12554251

申请日：2009-09-04

Applicant: Toshiyuki KAWAGUCHI ,  Kazutoki TAHARA ,  Tsutomu SAGA

Inventor： Toshiyuki KAWAGUCHI ,  Kazutoki TAHARA ,  Tsutomu SAGA

IPC: H04B10/02

CPC classification number: H05K1/147 ,  H05K1/0234 ,  H05K1/0237 ,  H05K1/0393 ,  H05K1/167 ,  H05K1/189 ,  H05K2201/049 ,  H05K2201/055 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2201/09972 ,  H05K2201/10121

Abstract: An optical transceiver of the present invention comprising an OSA, a circuit board, and a flexible substrate connecting these, in which the flexible substrate has high-speed signal lines and other lines other than the high speed signal lines provided separated from each other on the same surface, a ground layer placed apart and opposite these, and a resistive layer placed apart and opposite the high-speed signal lines, the other lines and the ground layer. High-speed signal and the resistive layer are opposite at least a part of the other lines.

Abstract translation: 本发明的光收发器包括OSA，电路板和连接它们的柔性基板，其中柔性基板具有高速信号线和除了高速信号线之外的其它线路，所述高速信号线彼此分离， 相同的表面，与这些放置分离并相对的接地层，以及与高速信号线，其他线路和接地层分开并相对的电阻层。 高速信号和电阻层与其他线路的至少一部分相对。