公开(公告)号：US10076031B2

公开(公告)日：2018-09-11

申请号：US14519331

申请日：2014-10-21

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Atsushi Kozuki ,  Hideshi Hamada ,  Yoshifumi Yoshida

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/00 ,  H05K1/18 ,  H05K1/09 ,  H05K3/40 ,  B81B7/00 ,  H05K1/03 ,  H05K3/10 ,  H01L23/055

CPC classification number: H05K1/09 ,  B81B7/007 ,  H01L23/055 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/16152 ,  H05K1/0306 ,  H05K1/181 ,  H05K3/108 ,  H05K3/4007 ,  H05K3/4046 ,  H05K2201/0338 ,  H05K2201/0347 ,  H05K2201/10287 ,  H01L2224/0401

Abstract: An electronic device includes an insulating base substrate having a through electrode, an electronic element provided on one surface of the insulating base substrate and connected to the through electrode, a lid provided on the one surface of the insulating base substrate, and an external electrode covering an end face of the through electrode that is exposed on another surface of the insulating base substrate different from the one surface thereof. The external electrode has a conductive film, a first electrolytic plating film provided on the conductive film, and a second electrolytic plating film provided on the first electrolytic plating film. The conductive film is provided on the exposed end face of the through electrode and on portions of the another surface of the insulating base substrate in the vicinity of the exposed end face of the through electrode.

公开(公告)号：US20180220527A1

公开(公告)日：2018-08-02

申请号：US15940314

申请日：2018-03-29

Applicant: DELL PRODUCTS, LP

Inventor： Stuart Allen Berke ,  Sandor Farkas ,  Bhyrav M. Mutnury

IPC: H05K1/02 ,  H05K3/42 ,  H05K1/09

CPC classification number: H05K1/0251 ,  H05K1/09 ,  H05K3/429 ,  H05K2201/0338 ,  H05K2201/09509 ,  H05K2201/09536 ,  Y10T29/49004

Abstract: A printed circuit board includes a first trace, a second trace, and a first via. The first trace is in a first conductive layer. The second trace is in a second conductive layer. The first via interconnects the first trace and the second trace, and communicates a first signal from the first trace to the second trace through a third conductive layer. The third conductive layer has a higher impedance than the first conductive layer and the second conductive layer.

公开(公告)号：US20180160528A1

公开(公告)日：2018-06-07

申请号：US15578484

申请日：2015-10-30

Applicant: MEIKO ELECTRONICS CO., LTD.

Inventor： Shigeru MICHIWAKI

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K3/14 ,  H05K3/00

CPC classification number: H05K1/0284 ,  H05K1/0326 ,  H05K1/09 ,  H05K3/0014 ,  H05K3/0023 ,  H05K3/14 ,  H05K3/181 ,  H05K3/389 ,  H05K3/426 ,  H05K2201/0129 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/09118 ,  H05K2203/072 ,  H05K2203/124 ,  H05K2203/1461

Abstract: A three-dimensional wiring board production method is provided that includes: a preparation step of preparing a resin film having a breaking elongation of 50% or more; a first metal film formation step of forming a first metal film on a surface of the resin film; a pattern formation step of performing patterning on the first metal film to form a desired pattern; a three-dimensional molding step of performing three-dimensional molding by heating and pressurizing the resin film; and a second metal film formation step of forming a second metal film on the first metal film having a pattern formed thereon. In the first metal film formation step, metal is deposited in a particle state to form the first metal film in a porous state.

公开(公告)号：US09980371B2

公开(公告)日：2018-05-22

申请号：US15044380

申请日：2016-02-16

Applicant: IBIDEN CO., LTD.

Inventor： Takayuki Katsuno ,  Yuki Ito ,  Takeshi Furusawa ,  Takema Adachi

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/00 ,  H05K3/24 ,  H05K3/02 ,  H05K3/18

CPC classification number: H05K1/0271 ,  H05K3/007 ,  H05K3/025 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/098 ,  H05K2203/1184

Abstract: A printed wiring board includes a resin insulating layer having recess portions formed on first surface, a first conductor layer formed in the recess portions and including pads positioned to mount an electronic component, conductive pillars formed on the pads, respectively, and formed to mount the electronic component onto the resin insulating layer, a second conductor layer formed on second surface of the resin insulating layer on the opposite side with respect to the first surface, and a via conductor formed in the resin insulating layer such that the via conductor is penetrating through the resin insulating layer and connecting the first and second conductor layers. The pillars is formed such that each of the pads has an exposed surface exposed from a respective one of the conductive pillars, and the pads are formed such that the exposed surface is recessed from the first surface of the resin insulating layer.

公开(公告)号：US20180124925A1

公开(公告)日：2018-05-03

申请号：US15572506

申请日：2016-06-01

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD. ,  SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.

Inventor： Kayo HASHIZUME ,  Yoshio OKA ,  Takashi KASUGA ,  Jinjoo PARK ,  Hiroshi UEDA

IPC: H05K3/38 ,  B32B15/20 ,  B32B15/088 ,  H05K1/09 ,  H05K3/46

CPC classification number: H05K3/388 ,  B32B15/08 ,  B32B15/088 ,  B32B15/20 ,  B32B2307/202 ,  B32B2457/08 ,  H05K1/09 ,  H05K1/097 ,  H05K3/022 ,  H05K3/381 ,  H05K3/4644 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2203/0766 ,  H05K2203/0793 ,  H05K2203/095

Abstract: According to an embodiment of the present invention, a substrate for a printed circuit board, the substrate including a resin film and a metal layer deposited on at least one surface of the resin film, includes a modified layer on the surface of the resin film on which the metal layer is deposited, the modified layer having a composition different from another portion, in which the modified layer contains a metal, a metal ion, or a metal compound different from a main metal of the metal layer. The content of a metal element of the metal, the metal ion, or the metal compound on a surface of the modified layer is preferably 0.2 atomic % or more and 10 atomic % or less.

公开(公告)号：US09955577B2

公开(公告)日：2018-04-24

申请号：US15133352

申请日：2016-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin Cho ,  Hyeon Cheol Park ,  Kwanghee Kim ,  Weonho Shin ,  Daejin Yang

IPC: H05K1/09 ,  H05K1/02 ,  H01L51/52 ,  G06F3/047

CPC classification number: H05K1/09 ,  G06F3/041 ,  G06F3/047 ,  G06F2203/04102 ,  H01B1/02 ,  H01B1/023 ,  H01B1/026 ,  H01B1/16 ,  H01L51/5206 ,  H01L51/5234 ,  H01L2251/301 ,  H01L2251/5338 ,  H05K1/0274 ,  H05K2201/0108 ,  H05K2201/0323 ,  H05K2201/0338 ,  H05K2201/0373 ,  H05K2201/0379 ,  H05K2201/0391 ,  H05K2201/09681 ,  H05K2201/10128

Abstract: A conductive component including: a substrate, a first layer comprising a plurality of island structures disposed on the substrate, wherein the island structures include graphene; and a second layer disposed on the first layer, wherein the second layer includes a plurality of conductive nanowires. Also, an electronic device including the conductive component.

公开(公告)号：US09955568B2

公开(公告)日：2018-04-24

申请号：US14163389

申请日：2014-01-24

Applicant: Dell Products, LP

Inventor： Stuart Allen Berke ,  Sandor Farkas ,  Bhyrav M. Mutnury

IPC: H05K3/42 ,  H05K1/02 ,  H05K1/09

CPC classification number: H05K1/0251 ,  H05K1/09 ,  H05K3/429 ,  H05K2201/0338 ,  H05K2201/09509 ,  H05K2201/09536 ,  Y10T29/49004

Abstract: A printed circuit board includes a first trace, a second trace, and a first via. The first trace is in a first conductive layer. The second trace is in a second conductive layer. The first via interconnects the first trace and the second trace, and communicates a first signal from the first trace to the second trace through a third conductive layer. The third conductive layer has a higher impedance than the first conductive layer and the second conductive layer.

公开(公告)号：US20180110133A1

公开(公告)日：2018-04-19

申请号：US15784070

申请日：2017-10-13

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Douglas Ward Thomas

IPC: H05K3/46 ,  H05K3/00 ,  H05K1/14 ,  H05K3/40 ,  H05K1/11 ,  H05K3/10

CPC classification number: H01H85/12 ,  H01H85/0013 ,  H01H85/055 ,  H01H85/06 ,  H01H85/143 ,  H01H85/20 ,  H01H85/306 ,  H01H85/56 ,  H01H2001/5877 ,  H01H2085/025 ,  H01H2085/0555 ,  H05K1/115 ,  H05K1/144 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/108 ,  H05K3/4076 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/0338 ,  H05K2201/041 ,  H05K2201/09227 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/1438 ,  H05K2203/166 ,  Y10T29/49165

Abstract: A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.

公开(公告)号：US20180108506A1

公开(公告)日：2018-04-19

申请号：US15730054

申请日：2017-10-11

Applicant: Littelfuse, Inc.

Inventor： Michael Doering ,  Pascal Jung

IPC: H01H85/12 ,  H01H85/20 ,  H01H85/30 ,  H01H85/56 ,  H01H85/055

CPC classification number: H01H85/12 ,  H01H85/0013 ,  H01H85/02 ,  H01H85/055 ,  H01H85/06 ,  H01H85/143 ,  H01H85/20 ,  H01H85/306 ,  H01H85/56 ,  H01H2001/5877 ,  H01H2085/025 ,  H01H2085/0555 ,  H05K1/115 ,  H05K1/144 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/108 ,  H05K3/4076 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/0338 ,  H05K2201/041 ,  H05K2201/09227 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/1438 ,  H05K2203/166

Abstract: Fuse assemblies are disclosed. In one implementation, a fuse assembly may be disposed that includes a first portion of the second portion. The first portion may be formed of a first metal. The second portion may be formed of a second metal different from the first metal. The second metal may be copper, and the copper may be tin plated or silver plated.

公开(公告)号：US09913383B2

公开(公告)日：2018-03-06

申请号：US15594778

申请日：2017-05-15

Applicant: LG INNOTEK CO., LTD.

Inventor： Yun Mi Bae ,  Soon Gyu Kwon ,  Sang Hwa Kim ,  Sang Young Lee ,  Jin Hak Lee ,  Han Su Lee ,  Dong Hun Jeong ,  In Ho Jeong ,  Dae Young Choi ,  Jung Ho Hwang

IPC: H05K1/09 ,  H05K3/24 ,  H05K3/18 ,  C25D5/48 ,  C25D5/02 ,  C25D3/38 ,  C25D3/48 ,  C25D7/12

CPC classification number: H05K1/11 ,  C25D3/38 ,  C25D3/48 ,  C25D5/022 ,  C25D5/48 ,  C25D7/123 ,  H05K1/09 ,  H05K3/108 ,  H05K3/181 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/098 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2203/1184

Abstract: A printed circuit board includes: an insulating layer; a plating seed layer disposed on the insulating layer; a circuit pattern layer disposed on the plating seed layer and formed of copper (Cu); and a surface treatment layer disposed on the circuit pattern layer and formed of gold (Au), wherein a width of a bottom surface of the surface treatment layer is narrower than a width of a top surface of the plating seed layer, wherein the bottom surface of the surface treatment layer includes: a first portion contacted with the circuit pattern layer; and a second portion non contacted with the circuit pattern layer, and wherein a width of a top surface of the circuit pattern layer is narrower than a width of a bottom surface of the circuit pattern layer.