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    High density interconnect substrate
    141.
    发明授权
    High density interconnect substrate 失效
    高密度互连基板

    公开(公告)号：US5891795A

    公开(公告)日：1999-04-06

    申请号：US617156

    申请日：1996-03-18

    Applicant: John K. Arledge ,  Thomas J. Swirbel

    Inventor： John K. Arledge ,  Thomas J. Swirbel

    IPC: H01L21/48 ,  H05K3/40 ,  H05K3/46 ,  H01L21/44 ,  H01L23/48

    CPC classification number: H05K3/4046 ,  H01L21/4846 ,  H01L21/4853 ,  H01L2924/0002 ,  H05K2201/0347 ,  H05K2201/10234 ,  H05K3/4644

    Abstract: A method of creating high density interlayer interconnects on circuit carrying substrates. A circuit pattern (20) is formed on one side of a substrate (10), and gold balls (30) are selectively placed on the circuit pattern using a thermosonic ball bonder. A liquid solution of a polymer is cast directly on the substrate and the etched circuit pattern such that only the upper portion of each gold ball is revealed when the liquid polymer solution is then dried and cured to form a dry film (40). A second layer of metal is then deposited directly on the dry film, such that it is electrically and mechanically connected to the exposed top of the gold balls. A second circuit pattern (50) is then formed in the second layer of metal. The resulting high density interconnect has two circuit layers separated by a dielectric layer. Each circuit layer is connected to the other by the gold balls that serve as conductive vias.

    Abstract translation: 一种在电路承载衬底上产生高密度层间互连的方法。 电路图案（20）形成在基板（10）的一侧上，并且使用热球球接合器将金球（30）选择性地放置在电路图案上。 将聚合物的液体溶液直接浇铸在基材和蚀刻电路图案上，使得仅当液体聚合物溶液干燥和固化以形成干膜（40）时，才会露出每个金球的上部。 然后将第二层金属直接沉积在干膜上，使得其与金球的暴露的顶部电气和机械连接。 然后在第二金属层中形成第二电路图案（50）。 所得到的高密度互连具有由介电层隔开的两个电路层。 每个电路层通过用作导电通孔的金球彼此连接。

    "> Method for producing laminated film/metal structures for known good die (
    147.
    发明授权
    Method for producing laminated film/metal structures for known good die ("KG") applications 失效
    用于生产已知的良好模具（“KGD”）应用的层压薄膜/金属结构的方法

    公开(公告)号：US5776824A

    公开(公告)日：1998-07-07

    申请号：US577187

    申请日：1995-12-22

    Applicant: Warren M. Farnworth ,  David R. Hembree

    Inventor： Warren M. Farnworth ,  David R. Hembree

    IPC: H01L21/48 ,  H05K3/00 ,  H05K3/06 ,  H05K3/40 ,  H05K3/42 ,  H01L21/441

    CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H05K2201/0154 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/135 ,  H05K3/002 ,  H05K3/064 ,  H05K3/423 ,  Y02P80/30 ,  Y10S428/901 ,  Y10T428/31681

    Abstract: A process for producing laminated film/metal structures comprising bumped circuit traces on a non-conductive substrate wherein a copper sheet/polyimide film laminate is coated with resist on the exterior surfaces. The resist adjacent the polyimide film is selectively exposed and etched to expose an area of the polyimide film. The exposed polyimide film is etched to form vias through the polyimide film to the inner side of the copper sheet. The resist adjacent the polyimide film is stripped away and a metal bump is electrolytically plated through each via onto the copper sheet. A subsequent layer of resist is electrophoretically applied over the bumps. The resist material adjacent the copper sheet is then selectively exposed and etched to expose areas of the copper sheet. The exposed copper sheet is etched to form circuit traces and the remaining resist adjacent both the polyimide film and the copper sheet is stripped away.

    Abstract translation: 一种在非导电性基板上形成有凸起电路迹线的叠层膜/金属结构体的制造方法，其中铜片/聚酰亚胺膜层叠体在外表面上涂有抗蚀剂。 选择性地暴露和蚀刻邻近聚酰亚胺膜的抗蚀剂以暴露聚酰亚胺膜的区域。 蚀刻暴露的聚酰亚胺膜，以通过聚酰亚胺膜形成通孔至铜片的内侧。 剥离与聚酰亚胺膜相邻的抗蚀剂，并通过每个通孔将金属凸块电镀到铜片上。 随后的抗蚀剂层电泳施加在凸块上。 然后选择性地暴露和蚀刻邻近铜片的抗蚀剂材料以暴露铜片的区域。 将曝光的铜片蚀刻以形成电路迹线，并将与聚酰亚胺膜和铜片相邻的剩余抗蚀剂剥离。

    Method of making a circuitized substrate
    148.
    发明授权
    Method of making a circuitized substrate 失效
    制造电路化基板的方法

    公开(公告)号：US5766499A

    公开(公告)日：1998-06-16

    申请号：US638251

    申请日：1996-04-26

    Applicant: Kim Joseph Blackwell ,  Daniel Peter Labzentis ,  Jonathan David Reid

    Inventor： Kim Joseph Blackwell ,  Daniel Peter Labzentis ,  Jonathan David Reid

    IPC: H01L21/48 ,  H05K1/02 ,  H05K3/00 ,  H05K3/06 ,  H05K3/24 ,  H05K3/30 ,  H05K3/40 ,  H05K3/42 ,  H01L21/02

    CPC classification number: H05K3/002 ,  H01L21/4857 ,  H05K1/0266 ,  H05K3/4007 ,  H05K2201/0166 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/09063 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2203/0554 ,  H05K2203/1476 ,  H05K2203/167 ,  H05K3/0008 ,  H05K3/062 ,  H05K3/243 ,  H05K3/303 ,  H05K3/427

    Abstract: A method of making a circuitized substrate wherein a dielectric layer is provided having a first layer of metallic material thereon. A first metallic member is formed on the dielectric's metallic layer, following which a pair of openings are precisely provided within a second dielectric material located on the dielectric. These openings in turn define a selected area on the first metallic member and, significantly, a precisely oriented pattern of the first metallic layer at a spaced distance from the metallic member. This metallic pattern serves as a mask to permit formation of an opening through the dielectric, which opening in turn may be engaged by tooling or the like such as may be used to position an electronic component, e.g., semiconductor device, on the underlying substrate. The invention thus assures precise orientation and placement of components such as semiconductor devices on highly dense circuit patterns such as those required in the present art in the manufacture of devices such as those of the information handling system (computer) variety.

    Abstract translation: 一种制造电路化基板的方法，其中提供介电层，其上具有第一层金属材料。 第一金属构件形成在电介质的金属层上，随后在位于电介质上的第二电介质材料内精确地设置一对开口。 这些开口依次限定第一金属构件上的选定区域，并且显着地限定第一金属层与金属构件隔开距离的精确定向图案。 该金属图案用作掩模以允许通过电介质形成开口，该开口又可以通过工具等接合，例如可用于将电子部件（例如半导体器件）定位在下面的基板上。 因此，本发明确保了诸如半导体器件之类的部件在诸如本领域所需要的诸如信息处理系统（计算机）品种的设备的制造中的高密度电路图案上的精确取向和放置。

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