公开(公告)号：US07968803B2

公开(公告)日：2011-06-28

申请号：US11658877

申请日：2006-07-07

Applicant: Hideki Higashitani

Inventor： Hideki Higashitani

IPC: H05K1/11

CPC classification number: H05K3/4069 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/384 ,  H05K3/4614 ,  H05K3/465 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0373 ,  H05K2201/09827 ,  H05K2203/025 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/1461 ,  Y10T29/49124

Abstract: A wiring substrate of the invention comprises an electrical insulation substrate (1), a through-hole (3) formed in the electrical insulation substrate, electrically conductive paste (4) filled inside the through-hole, and wiring traces (11) formed on one or both surfaces of the electrical insulation substrate and electrically connected with the electrically conductive paste, wherein interfaces of the wiring traces in contact with the electrically conductive paste have at least one of an asperate surface and a smooth surface, and a plurality of granular bumps (14) formed further thereon.

Abstract translation: 本发明的布线基板包括电绝缘基板（1），形成在电绝缘基板中的通孔（3），填充在通孔内部的导电浆料（4）和形成在通孔 电绝缘基板的一个或两个表面并与导电浆料电连接，其中与导电浆料接触的布线迹线的界面具有平坦表面和光滑表面中的至少一个，以及多个颗粒凸块 （14）。

公开(公告)号：US20110121445A1

公开(公告)日：2011-05-26

申请号：US13055372

申请日：2009-07-23

Applicant: Kentaro Mori ,  Hideya Murai ,  Shintaro Yamamichi ,  Masaya Kawano ,  Koji Soejima

Inventor： Kentaro Mori ,  Hideya Murai ,  Shintaro Yamamichi ,  Masaya Kawano ,  Koji Soejima

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/34 ,  H01L21/44

CPC classification number: H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/115 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/10674 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/063 ,  H05K2203/1469 ,  H01L2924/00

Abstract: A semiconductor device includes a plural number of interconnects and a plural number of vias are stacked. A semiconductor element is enclosed in an insulation layer. At least one of the vias provided in insulation layers and/or at least one of interconnects provided in the interconnect layers are of cross-sectional shapes different from those of the vias formed in another one of the insulation layers and/or interconnects provided in another one of the interconnect layers.

Abstract translation: 半导体器件包括多个互连件，并且堆叠多个通孔。 半导体元件封装在绝缘层中。 提供在绝缘层中的至少一个通孔和/或设置在互连层中的至少一个互连件的横截面形状与在另一个绝缘层中提供的另一个绝缘层和/或互连中形成的通孔的截面形状不同 互连层之一。

公开(公告)号：US07948076B2

公开(公告)日：2011-05-24

申请号：US12557541

申请日：2009-09-11

Applicant: Chia-Chung Wang ,  Charles W. C. Lin

Inventor： Chia-Chung Wang ,  Charles W. C. Lin

IPC: H01L23/10 ,  H01L23/34

CPC classification number: H05K1/0206 ,  H01L23/3677 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L33/483 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/12041 ,  H01L2924/181 ,  H05K1/112 ,  H05K3/06 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/10106 ,  H05K2201/10553 ,  H05K2203/0369 ,  H05K2203/049 ,  H05K2203/0733 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a substrate and an adhesive. The semiconductor device is electrically connected to the substrate and thermally connected to the heat spreader. The heat spreader includes a post and a base. The post extends upwardly through an opening in the adhesive into an aperture in the substrate, and the base extends laterally and supports the substrate. The adhesive extends between the post and the substrate and between the base and the substrate. The substrate includes first and second conductive layers and a dielectric layer therebetween, and the assembly provides vertical signal routing between a pad at the first conductive layer and a terminal below the adhesive.

Abstract translation: 半导体芯片组件包括半导体器件，散热器，衬底和粘合剂。 半导体器件电连接到衬底并热连接到散热器。 散热器包括一个柱子和一个底座。 该柱向上穿过粘合剂中的开口延伸到基底中的孔中，并且基部横向延伸并支撑基底。 粘合剂在柱和基底之间以及基底和基底之间延伸。 衬底包括第一和第二导电层以及它们之间的电介质层，并且该组件提供在第一导电层处的焊盘和粘合剂下面的端子之间的垂直信号路由。

公开(公告)号：US20110108984A1

公开(公告)日：2011-05-12

申请号：US13004242

申请日：2011-01-11

Applicant: Wen-Yuan Chang ,  Wei-Cheng Chen ,  Yeh-Chi Hsu

Inventor： Wen-Yuan Chang ,  Wei-Cheng Chen ,  Yeh-Chi Hsu

IPC: H01L23/498 ,  H05K1/09

CPC classification number: H05K3/242 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2203/054 ,  H05K2203/0723 ,  H01L2224/05099

Abstract: A circuit board includes a substrate that has a top surface and a base surface opposite to each other, at least a top pad disposed on the top surface, a top solder resist layer disposed on the top surface and covering a portion of the top pad, and a pre-bump disposed on the top pad. The top solder resist layer has a first opening exposing a portion of the top pad. The pre-bump is located in the first opening and has a protrusion protruding from the top solder resist layer. A maximum width of the protrusion is less than or equal to a width of the top pad. A chip package structure having the circuit board is also provided.

Abstract translation: 电路板包括具有彼此相对的顶表面和底表面的基底，至少设置在顶表面上的顶垫，设置在顶表面上并覆盖顶垫的一部分的顶部阻焊层， 以及设置在顶垫上的预凸块。 顶部阻焊层具有暴露顶部焊盘的一部分的第一开口。 预凸块位于第一开口中并且具有从顶部阻焊层突出的突起。 突起的最大宽度小于或等于顶垫的宽度。 还提供了具有电路板的芯片封装结构。

公开(公告)号：US07888803B2

公开(公告)日：2011-02-15

申请号：US11580928

申请日：2006-10-16

Applicant: Takashi Kariya ,  Hironori Tanaka

Inventor： Takashi Kariya ,  Hironori Tanaka

IPC: H01L23/48

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09827 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2224/05599

Abstract: A printed circuit board including a conductor portion, an insulating layer formed over the conductor portion, a thin-film capacitor formed over the insulating layer and including a first electrode, a second electrode and a high-dielectric layer interposed between the first electrode and the second electrode, and a via-hole conductor structure formed through the second electrode and insulating layer and electrically connecting the second electrode and the conductor portion. The via-hole conductor structure has a first portion in the second electrode and a second portion in the insulating layer. The first portion of the via-hole conductor structure has a truncated-cone shape tapering toward the conductor portion.

Abstract translation: 一种印刷电路板，包括导体部分，在导体部分上形成的绝缘层，形成在绝缘层之上的薄膜电容器，并且包括第一电极，第二电极和介于第一电极和第二电极之间的高电介质层 第二电极和通过第二电极和绝缘层形成的通孔导体结构，并且电连接第二电极和导体部分。 通孔导体结构在第二电极中具有第一部分，在绝缘层中具有第二部分。 通孔导体结构的第一部分具有朝向导体部分逐渐变细的截锥形。

公开(公告)号：US07847197B2

公开(公告)日：2010-12-07

申请号：US11968700

申请日：2008-01-03

Applicant: Yoshikazu Oikawa ,  Takayoshi Yoshikawa

Inventor： Yoshikazu Oikawa ,  Takayoshi Yoshikawa

IPC: H01R12/04 ,  H05K1/11 ,  H01K3/10

CPC classification number: H05K1/0265 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81385 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/0029 ,  H05K3/107 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0352 ,  H05K2201/09227 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/0156 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A multilayer circuit board includes a laminate having a plurality of ceramic layers, and a wiring pattern disposed in the laminate, wherein a ceramic layer includes, as the wiring pattern, a fully penetrating via-hole conductor that vertically passes through the ceramic layers, and a serial partially penetrating via-hole conductor that is electrically connected to the fully penetrating via-hole conductor in the ceramic layers and does not pass completely through the ceramic layers.

Abstract translation: 多层电路板包括具有多个陶瓷层的层压体和布置在层叠体中的布线图案，其中陶瓷层包括垂直穿过陶瓷层的完全穿透的通孔导体作为布线图案，以及 连接部分穿透的通孔导体，其电连接到陶瓷层中的完全穿透的通孔导体，并且不完全穿过陶瓷层。

公开(公告)号：US20100261348A1

公开(公告)日：2010-10-14

申请号：US12801723

申请日：2010-06-22

Applicant: Kyoung Ro Yoon ,  Young Hwan Shin ,  Yoon Su Kim ,  Tae Gon Lee

Inventor： Kyoung Ro Yoon ,  Young Hwan Shin ,  Yoon Su Kim ,  Tae Gon Lee

IPC: H01L21/768

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2924/0002 ,  H05K1/0265 ,  H05K3/06 ,  H05K3/243 ,  H05K3/28 ,  H05K3/427 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2203/0369 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package substrate, including: preparing a copper clad laminate and half etching a copper foil on a wire bonding pad side of the copper clad laminate; depositing a first etching resist on the opposite sides of the copper clad laminate; forming circuit patterns on the first etching resist, constructing circuits including a wire bonding pad and a ball pad after the model of the circuit patterns, and removing the first etching resist; applying a solder resist to the copper clad laminate in such a way to expose the wire bonding pad and the ball pad; and plating the wire bonding pad with gold and subjecting the ball pad to surface treatment.

Abstract translation: 一种半导体封装基板的制造方法，其特征在于，包括：在覆铜层压板的引线接合焊盘侧准备覆铜层压板并半铜蚀刻铜箔; 在覆铜层压板的相对侧上沉积第一蚀刻抗蚀剂; 在所述第一蚀刻抗蚀剂上形成电路图案，在所述电路图案的模型之后构造包括引线接合焊盘和球垫的电路，以及去除所述第一抗蚀剂; 以覆铜层压板的方式涂覆阻焊剂，以使引线接合焊盘和焊盘露出; 并用金焊接引线接合垫，并对球垫进行表面处理。

公开(公告)号：US07790503B2

公开(公告)日：2010-09-07

申请号：US11958603

申请日：2007-12-18

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

IPC: H01L21/00

CPC classification number: H01L23/50 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/20 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09736 ,  H05K2203/016 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing a semiconductor device includes providing a substrate with an insulation layer disposed on a top surface of the substrate, forming a passive device over the top surface of the substrate, removing the substrate, depositing an insulating polymer film layer over the insulation layer, and depositing a metal layer over the insulating polymer film layer. A solder mask can be formed over the metal layer. A conformal metal layer can then be formed over the solder mask. A notch can be formed in the insulation layer to enhance the connection between the insulating polymer film layer and the insulation layer. Additional semiconductor die can be electrically connected to the passive device. The substrate is removed by removing a first amount of the substrate using a back grind process, and then removing a second amount of the substrate using a wet dry, dry etch, or chemical-mechanical planarization process.

Abstract translation: 一种制造半导体器件的方法包括：在衬底的顶表面上设置绝缘层，在衬底的顶表面上形成无源器件，去除衬底，在绝缘层上沉积绝缘聚合物膜层 并且在绝缘聚合物膜层上沉积金属层。 可以在金属层上形成焊接掩模。 然后可以在焊接掩模上形成保形金属层。 可以在绝缘层中形成切口以增强绝缘聚合物膜层和绝缘层之间的连接。 另外的半导体管芯可以电连接到无源器件。 通过使用后研磨工艺去除第一量的基材，然后使用湿干，干蚀刻或化学机械平面化工艺除去第二量的基材来除去基材。

公开(公告)号：US07768116B2

公开(公告)日：2010-08-03

申请号：US11495649

申请日：2006-07-31

Applicant: Kyoung Ro Yoon ,  Young Hwan Shin ,  Yoon Su Kim ,  Tae Gon Lee

Inventor： Kyoung Ro Yoon ,  Young Hwan Shin ,  Yoon Su Kim ,  Tae Gon Lee

IPC: H01L23/02

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2924/0002 ,  H05K1/0265 ,  H05K3/06 ,  H05K3/243 ,  H05K3/28 ,  H05K3/427 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2203/0369 ,  H01L2924/00

Abstract: Disclosed herein are a semiconductor package substrate and a method for fabricating the same. In the semiconductor package substrate, the circuit layer of the wire bonding pad side differs in thickness from that of the ball pad side to which a half etching process is applied. In addition, a connection through hole is constructed to provide an electrical connection between the plating lead lines on the wire bonding pad side and the ball pad side, thereby preventing electrical disconnection when the plating lead line of the wire bonding pad side is cut.

Abstract translation: 本文公开了一种半导体封装基板及其制造方法。 在半导体封装基板中，引线接合焊盘侧的电路层的厚度与施加半蚀刻工序的焊盘侧的厚度不同。 此外，连接通孔被构造成在引线接合焊盘侧的电镀引线和焊盘侧之间提供电连接，从而防止当焊线焊盘侧的电镀引线被切断时的断电。

公开(公告)号：US20100122840A1

公开(公告)日：2010-05-20

申请号：US12694322

申请日：2010-01-27

Applicant: Motoo ASAI ,  Dongdong Wang ,  Takahiro Mori

Inventor： Motoo ASAI ,  Dongdong Wang ,  Takahiro Mori

IPC: H05K1/02 ,  H05K1/03

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board including a core structure including resin layers and conductor circuits sandwiched by the resin layers, the core structure having a first surface and a second surface on an opposite side of the first surface, a first conductor layer including conductor circuits formed on the first surface of the core structure, and a second conductor layer including conductor circuits formed on the second surface of the core structure. The core structure includes a first via hole and a second via hole, the first via hole and the second via hole sandwich one or more conductor circuits in the core substrate and are positioned vertically to form a through hole electrically connecting respective ones of the conductor circuits of the first and the second conductor layers, and the first via hole and the second via hole are deviated from each other in a vertical direction.

Abstract translation: 一种多层印刷电路板，包括由树脂层和由树脂层夹在的导体电路的芯结构，芯结构具有在第一表面的相对侧的第一表面和第二表面，第一导体层包括导体电路 形成在芯结构的第一表面上，以及第二导体层，包括形成在芯结构的第二表面上的导体电路。 芯结构包括第一通孔和第二通孔，第一通孔和第二通孔夹着芯基板中的一个或多个导体电路并垂直定位，以形成电连接各个导体电路的通孔 的第一和第二导体层，并且第一通孔和第二通孔在垂直方向上彼此偏离。