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    Patch panel and patch panel connector
    142.
    发明授权
    Patch panel and patch panel connector 失效
    配线架和接线板连接器

    公开(公告)号：US07677898B2

    公开(公告)日：2010-03-16

    申请号：US12023008

    申请日：2008-01-30

    Applicant: Yi Rui ,  Ai-Yu Pan ,  Jian-She Shen ,  Mei Huang

    Inventor： Yi Rui ,  Ai-Yu Pan ,  Jian-She Shen ,  Mei Huang

    IPC: H01R29/00

    CPC classification number: G06F13/4068 ,  G06F2213/0026 ,  H05K1/0237 ,  H05K1/0295 ,  H05K1/141 ,  H05K3/222 ,  H05K2201/044 ,  H05K2201/09227 ,  H05K2201/09954 ,  H05K2201/10189

    Abstract: An exemplary patch panel includes a printed circuit board having a plurality of signal terminals for connecting to two pairs of peripheral component interconnect express (PCI-E) X1 differential signal terminals of an I/O controller hub (ICH), an interface terminal of a high definition multimedia interface (HDMI), four pairs of differential signal terminals of the HDMI, four pairs of differential signal terminals of a graphic and memory controller hub (GMCH), one of another differential signal terminal of the GMCH, and two pairs of differential signal terminals of a PCI-E X16 slot. Therefore, the ICH is connected to the PCI-E X16 slot via the patch panel for supporting a PCI-E X1 card while the GMCH is connected to the HDMI via the patch panel. A patch panel connector is provided to mount the patch panel on a motherboard.

    Abstract translation: 示例性接线板包括具有多个信号端子用于连接到I / O控制器集线器（ICH）的两对外围组件互连快速（PCI-E）X1差分信号端子的印刷电路板， 高分辨率多媒体接口（HDMI），HDMI对的四对差分信号端子，图形和存储器控制器集线器（GMCH）的四对差分信号端子，GMCH的另一个差分信号端子和两对差分 PCI-E X16插槽的信号端子。 因此，ICH通过接线板连接到PCI-E X16插槽，用于支持PCI-E X1卡，而GMCH通过接线板连接到HDMI。 提供了一个接线板连接器，用于将接线板安装在主板上。

    S-TURN VIA AND METHOD FOR REDUCING SIGNAL LOSS IN DOUBLE-SIDED PRINTED WIRING BOARDS
    145.
    发明申请
    S-TURN VIA AND METHOD FOR REDUCING SIGNAL LOSS IN DOUBLE-SIDED PRINTED WIRING BOARDS 审中-公开
    S-TURN通风及减少双面印刷线路信号损失的方法

    公开(公告)号：US20090159326A1

    公开(公告)日：2009-06-25

    申请号：US11960398

    申请日：2007-12-19

    Applicant: Richard Mellitz

    Inventor： Richard Mellitz

    IPC: H05K1/11 ,  G06F17/50

    CPC classification number: H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09627 ,  H05K2201/10189 ,  H05K2203/1572

    Abstract: Embodiments of the invention include a Printed Wiring Board (PWB) having a first via connected to a top-side signal source, a second via connected to a bottom-side signal destination, and a third via connected to the first via on a lower signal layer of the PWB and further connected to the second via on an upper signal layer of the PWB. In embodiments of the invention, the third via is referred to as an S-Turn via. The S-Turn PWB routing configuration advantageously reduces reflections causes by via stubs at Multi-Giga Hertz (MGH) frequencies. Other embodiments are described.

    Abstract translation: 本发明的实施例包括具有连接到顶侧信号源的第一通孔的印刷布线板（PWB），连接到底侧信号目的地的第二通孔和连接到下侧信号的第一通孔的第三通孔 层，并且在PWB的上信号层上进一步连接到第二通孔。 在本发明的实施例中，第三通孔被称为S转弯通孔。 S-Turn PWB路由配置有利于减少通过多千兆赫兹（MGH）频率的存根造成的反射。 描述其他实施例。

    Memory system having memory devices on two sides
    146.
    发明授权
    Memory system having memory devices on two sides 有权
    存储器系统具有两侧的存储器件

    公开(公告)号：US07523246B2

    公开(公告)日：2009-04-21

    申请号：US11681390

    申请日：2007-03-02

    Applicant: Haw-Jyh Liaw ,  David Nguyen

    Inventor： Haw-Jyh Liaw ,  David Nguyen

    IPC: G06F13/42

    CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

    Abstract: A memory system includes a first signal line to carry a first signal that enters the module at a first end of the first signal line and a second signal line to carry a second signal that enters the module at a first end of the second signal line. The module includes a first memory device disposed on a first side of the module and a second memory module disposed on a second side of the module positioned opposite to the first side. The first memory device and the second memory device are connected to the first signal line and the second signal line. The first signal and the second signal traverse alongside each other to arrive in turn at the first memory device and the second memory device. The system may include a controller that provides the first signal and the second signal.

    Abstract translation: 存储器系统包括：第一信号线，用于承载在第一信号线的第一端进入模块的第一信号;以及第二信号线，用于承载在第二信号线的第一端进入模块的第二信号。 模块包括设置在模块的第一侧上的第一存储器件和设置在与第一侧相对定位的模块的第二侧上的第二存储器模块。 第一存储器件和第二存储器件连接到第一信号线和第二信号线。 第一信号和第二信号彼此并行地依次移动以在第一存储器件和第二存储器件上依次进入。 该系统可以包括提供第一信号和第二信号的控制器。

    Memory system having a clock line and termination
    147.
    发明授权
    Memory system having a clock line and termination 有权
    具有时钟线和终端的存储系统

    公开(公告)号：US07519757B2

    公开(公告)日：2009-04-14

    申请号：US11691406

    申请日：2007-03-26

    Applicant: Haw-Jyh Liaw ,  David Nguyen

    Inventor： Haw-Jyh Liaw ,  David Nguyen

    IPC: G06F13/42

    CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

    Abstract: A memory system includes a controller chip and a memory module coupled to the controller chip. A signal line carries a signal that traverses the signal line until reaching a termination at an end of the signal line. A clock line carries a clock signal that traverses the clock line to reach a second termination at an end of the clock line. The module includes a first memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the first memory device at substantially the same time. The module includes a second memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the second memory device at substantially the same time and after the signal and the clock signal arrive at the first memory device.

    Abstract translation: 存储器系统包括控制器芯片和耦合到控制器芯片的存储器模块。 信号线承载穿过信号线的信号，直到在信号线的末端达到终止。 时钟线承载穿过时钟线的时钟信号，以在时钟线的末端到达第二个终端。 模块包括连接到信号线和时钟线的第一存储器件，使得信号和时钟信号在基本相同的时间到达第一存储器件。 模块包括连接到信号线和时钟线的第二存储器件，使得信号和时钟信号在基本上相同的时间到达第二存储器件，并且在信号和时钟信号到达第一存储器件之后。

    Main board for backplane buses
    148.
    发明授权
    Main board for backplane buses 失效
    背板总线主板

    公开(公告)号：US07505285B2

    公开(公告)日：2009-03-17

    申请号：US11404912

    申请日：2006-04-17

    Applicant: Hideki Osaka

    Inventor： Hideki Osaka

    IPC: H01R12/16

    CPC classification number: H05K1/0236 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/167 ,  H05K2201/044 ,  H05K2201/09681 ,  H05K2201/0969

    Abstract: A motherboard for backplane buses is provided that reduces noise due to entry of external signals into signal wiring which interconnects modules, or noise due to any external signals entering a power supply after being routed around the power supply.An EBG pattern formed up of two wiring regions different from each other in impedance is periodically disposed in at least three arrays as part of the power supply layer(s) constituting a microstripline structure (one layer adjacent to a signal layer is a power supply layer, and the other layer is interposed in air) or a stripline structure (both layers adjacent to a signal layer are power supply layers); the part of the power supply layer(s) not being involved in signal transmission between the modules on the motherboard for backplane buses.

    Abstract translation: 提供了用于背板总线的主板，其将由于外部信号进入到互连模块的信号布线而引起的噪声，或者由于任何外部信号在绕过电源而进入电源之后产生的噪声。 由构成微带结构的电源层的一部分（至少与信号层相邻的一层是供电层），在至少三个阵列中周期性地设置由阻抗彼此不同的两个布线区域形成的EBG图案 ，另一层插入空气）或带状线结构（与信号层相邻的两层是电源层）; 电源层的一部分不涉及用于背板总线的主板上的模块之间的信号传输。

    Electronic Board Arrangement and Electronic Interconnect Board of an Electronic Board Arrangement
    149.
    发明申请
    Electronic Board Arrangement and Electronic Interconnect Board of an Electronic Board Arrangement 失效
    电子板安排和电子板安排电子互连委员会

    公开(公告)号：US20090067146A1

    公开(公告)日：2009-03-12

    申请号：US12205492

    申请日：2008-09-05

    Applicant: Harald Huels ,  Dieter Staiger

    Inventor： Harald Huels ,  Dieter Staiger

    IPC: H01R12/16

    CPC classification number: H05K1/14 ,  H01R12/52 ,  H01R12/737 ,  H05K1/144 ,  H05K7/1458 ,  H05K7/1492 ,  H05K2201/044

    Abstract: The invention relates to an electronic-board arrangement, comprising at least two electronic boards (110, 110a-110n), particularly integrated circuit boards, which are attached to a backplane (10) which provides electrical interconnection between the at least two electronic boards (110, 110a-110n). An electronic interconnect board (40) providing electrical interconnect between the at least two electronic boards (110, 110a-110n) is arranged in a space (90) in between the at least two electronic boards (110, 110a-110n) and the backplane (10).

    Abstract translation: 本发明涉及一种电子板装置，其包括至少两个电子板（110,110〜110n），特别是集成电路板，其连接到背板（10），背板（10）提供至少两个电子板之间的电互连 110，110a-110n）。 在至少两个电子板（110,1 110a-110n）之间的空间（90）中，在至少两个电子板（110,1 110a-110n）之间提供电互连的电子互连板（40） （10）。

    MIDPLANE ESPECIALLY APPLICABLE TO AN ORTHOGONAL ARCHITECTURE ELECTRONIC SYSTEM
    150.
    发明申请
    MIDPLANE ESPECIALLY APPLICABLE TO AN ORTHOGONAL ARCHITECTURE ELECTRONIC SYSTEM 有权
    MIDPLANE特别适用于正交建筑电子系统

    公开(公告)号：US20090061684A1

    公开(公告)日：2009-03-05

    申请号：US12203270

    申请日：2008-09-03

    Applicant: Thomas S. Cohen ,  Marc B. Cartier, JR. ,  Mark W. Gailus

    Inventor： Thomas S. Cohen ,  Marc B. Cartier, JR. ,  Mark W. Gailus

    IPC: H01R24/00 ,  H01R13/648

    CPC classification number: H05K7/1445 ,  H01R13/514 ,  H01R13/6587 ,  H01R13/6591 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/14 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09718 ,  H05K2201/10189 ,  H05K2203/1572

    Abstract: A midplane has a first side to which contact ends of a first differential connector are connected and a second side opposite the first side to which contact ends of a second differential connector are connected. The midplane includes a plurality of vias extending from the first side to the second side, with the vias providing first signal launches on the first side and second signal launches on the second side. The first signal launches are provided in a plurality of rows, with each row having first signal launches along a first line and first signal launches along a second line substantially parallel to the first line. The second signal launches are provided in a plurality of columns, with each column having second signal launches along a third line and second signal launches along a fourth line substantially parallel to the third line.

    Abstract translation: 中平面具有连接第一差分连接器的接触端的第一侧和与第二差分连接器的接触端连接的第一侧相对的第二侧。 中平面包括从第一侧延伸到第二侧的多个通孔，其中通孔在第一侧上提供第一信号发射，而第二信号在第二侧上发射。 第一信号发射被设置成多行，每行具有沿着第一线的第一信号发射，并且第一信号沿着基本上平行于第一线的第二线发射。 第二信号发射被提供在多列中，每列具有沿着第三线的第二信号发射，而第二信号沿着基本上平行于第三线的第四线发射。

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