公开(公告)号：US5672414A

公开(公告)日：1997-09-30

申请号：US263332

申请日：1994-06-21

Applicant: Kenji Okamoto ,  Yukio Nakajima ,  Kazuhiko Imamura ,  Takao Ichihara

Inventor： Kenji Okamoto ,  Yukio Nakajima ,  Kazuhiko Imamura ,  Takao Ichihara

IPC: H05K3/46 ,  H01L23/12 ,  H01L23/24 ,  H01L23/538 ,  H01L25/16 ,  H05K1/05 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  B32B9/00

CPC classification number: H01L25/165 ,  H01L23/24 ,  H01L23/5383 ,  H01L25/162 ,  H05K1/141 ,  H05K1/144 ,  H05K1/147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/3025 ,  H05K1/056 ,  H05K1/182 ,  H05K1/189 ,  H05K2201/045 ,  H05K2203/1316 ,  H05K2203/302 ,  H05K3/363 ,  H05K3/368 ,  H05K3/4611 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A metallic printed board is formed by laminating an insulation layer on the surface of a metallic sheet as a base, and then electronic parts are mounted on the conductor pattern formed on the surface of the insulation layer. A double-sided printed board mounted thereon electronic parts is placed in parallel. Both the printed boards are supported and fixed monolithically by filling the space between the printed boards with an insulation resin and curing the resin. Furthermore, an insulation resin is laminated on the surface of the printed board in such a manner that the resin may cover the mounted electronic parts, and cured. The heat generated from the electronic parts can be efficiently transmitted to the insulation resins by using a resin having a high thermal conductivity for both of the insulation resins, and the heat is then emitted from the surfaces of the metallic sheet or the insulation resin.

Abstract translation: 通过在金属片的表面上层叠绝缘层作为基底而形成金属印刷电路板，然后将电子部件安装在形成在绝缘层的表面上的导体图案上。 将其上安装有电子部件的双面印刷电路平行放置。 通过用绝缘树脂填充印刷电路板之间的空间并固化树脂，两个印刷电路板被支撑和固定成一体。 此外，绝缘树脂层叠在印刷电路板的表面上，使得树脂可以覆盖所安装的电子部件并固化。 通过对两种绝缘树脂使用具有高导热性的树脂，从电子部件产生的热可以有效地传递到绝缘树脂，然后从金属片或绝缘树脂的表面发射热量。

公开(公告)号：US5502617A

公开(公告)日：1996-03-26

申请号：US444997

申请日：1995-05-19

Applicant: Katsumi Tsukada ,  Norio Nakamura ,  Minoru Nimura ,  Hiroyuki Suemori ,  Tomio Kamihata ,  Mutsuaki Yamazaki

Inventor： Katsumi Tsukada ,  Norio Nakamura ,  Minoru Nimura ,  Hiroyuki Suemori ,  Tomio Kamihata ,  Mutsuaki Yamazaki

IPC: G06K19/077 ,  G06F1/16 ,  G06F1/18 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H05K5/02 ,  H01R13/64 ,  H05K7/10

CPC classification number: G06F1/1656 ,  G06F1/16 ,  G06F1/1626 ,  G06F1/18 ,  H05K1/141 ,  H05K1/148 ,  H05K5/0269 ,  G06F2200/1631 ,  H05K1/181 ,  H05K2201/045 ,  H05K2201/10159 ,  H05K2201/10689 ,  H05K3/36 ,  H05K3/361

Abstract: A thin and small computer system that can be used generally for control equipment or the like, includes a CPU chip, peripheral control chips, and other components mounted in the form of a bare chip, whereby a computer system having a so-called ISA architecture can be incorporated in an IC card-like casing. Computer system components are fixedly attached to a double-sided printed wiring board. One side of the printed wiring board includes the CPU chip, an IO subsystem chip and memories and the other side includes an image control circuit, memories and the peripheral control chips. A 236-pin connector is formed on a long side of this card-type computer, and is connected to a control bus and an IO bus of the card-type computer. The control bus and the IO bus are not located at opposed positions in the connector. A position of separating the buses from each other is off the center of the connector. Power lines or ground lines are provided at the separating positions in the connector, thus preventing occurrence of unnecessary electromagnetic radiation noise.

Abstract translation: 可以通常用于控制设备等的薄型和小型计算机系统包括CPU芯片，外围控制芯片和以裸芯片形式安装的其他组件，由此具有所谓的ISA架构的计算机系统 可以结合在IC卡状外壳中。 计算机系统部件固定在双面印刷电路板上。 印刷电路板的一侧包括CPU芯片，IO子系统芯片和存储器，另一侧包括图像控制电路，存储器和外围控制芯片。 一个236针连接器形成在该卡型计算机的长边上，并连接到卡式计算机的控制总线和IO总线。 控制总线和IO总线不在连接器的相对位置。 将总线彼此分离的位置离开连接器的中心。 电源线或接地线设置在连接器的分离位置处，从而防止不必要的电磁辐射噪声的发生。

公开(公告)号：US5481432A

公开(公告)日：1996-01-02

申请号：US151214

申请日：1993-11-12

Applicant: Katsumi Tsukada ,  Norio Nakamura ,  Minoru Nimura ,  Hiroyuki Suemori ,  Tomio Kamihata ,  Mutsuaki Yamazaki

Inventor： Katsumi Tsukada ,  Norio Nakamura ,  Minoru Nimura ,  Hiroyuki Suemori ,  Tomio Kamihata ,  Mutsuaki Yamazaki

IPC: G06K19/077 ,  G06F1/16 ,  G06F1/18 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H05K5/02 ,  H01R13/64 ,  H05K7/10

CPC classification number: G06F1/1656 ,  G06F1/16 ,  G06F1/1626 ,  G06F1/18 ,  H05K1/141 ,  H05K1/148 ,  H05K5/0269 ,  G06F2200/1631 ,  H05K1/181 ,  H05K2201/045 ,  H05K2201/10159 ,  H05K2201/10689 ,  H05K3/36 ,  H05K3/361

Abstract: A thin and small computer system that can be used generally for control equipment or the like, includes a CPU chip, peripheral control chips, and other components mounted in the form of a bare chip, whereby a computer system having a so-called ISA architecture can be incorporated in an IC card-like casing. A 236-pin connector is formed on a long side of this card-type computer, and is connected to a control bus and an IO bus of the card-type computer. The control bus and the IO bus are not located at opposed positions in the connector. A position of separating the buses from each other is off the center of the connector. Power lines or ground lines are provided at the separating positions in the connector, thus preventing occurrence of unnecessary electromagnetic radiation noise. RAMs are mounted on a sub-PW board, which provides flexibility for the system. A bare chip of an EEPROM is mounted on another printed wiring board, which enables electrical forming to be performed after such mounting.

Abstract translation: 可以通常用于控制设备等的薄型和小型计算机系统包括CPU芯片，外围控制芯片和以裸芯片形式安装的其他组件，由此具有所谓的ISA架构的计算机系统 可以结合在IC卡状外壳中。 一个236针连接器形成在该卡型计算机的长边上，并连接到卡式计算机的控制总线和IO总线。 控制总线和IO总线不在连接器的相对位置。 将总线彼此分离的位置离开连接器的中心。 电源线或接地线设置在连接器的分离位置处，从而防止不必要的电磁辐射噪声的发生。 RAM安装在子PW板上，为系统提供灵活性。 EEPROM的裸芯片安装在另一印刷电路板上，这使得能够在这种安装之后执行电成形。

公开(公告)号：US4970577A

公开(公告)日：1990-11-13

申请号：US337145

申请日：1989-04-12

Applicant: Satoru Ogihara ,  Shunichi Numata ,  Kunio Miyazaki ,  Takashi Yokoyama ,  Ken Takahashi ,  Tasao Soga ,  Kazuji Yamada ,  Hiroichi Shinohara ,  Hideo Suzuki

Inventor： Satoru Ogihara ,  Shunichi Numata ,  Kunio Miyazaki ,  Takashi Yokoyama ,  Ken Takahashi ,  Tasao Soga ,  Kazuji Yamada ,  Hiroichi Shinohara ,  Hideo Suzuki

IPC: H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H01L23/52 ,  H01L23/64 ,  H05K1/02 ,  H05K1/03 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC classification number: H01L23/642 ,  H01L23/49827 ,  H01L23/49833 ,  H05K1/141 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01004 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15312 ,  H01L2924/16152 ,  H05K1/0271 ,  H05K1/0306 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/068 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K3/3426 ,  H05K3/368

Abstract: A semiconductor chip module includes semiconductor chips each of which has contacts on its entire front face. A multi-layered organic circuit board having a small dielectric constant is provided for mounting the semiconductor chips. Intermediate ceramic substrates having the same thermal expansion coefficient as that of the semiconductor chip, are also provided. Each such intermediate ceramic substrate has contacts on its front and back faces corresponding to those of the semiconductor chip. These contacts are electrically connected directly in a one-to-one relationship. The contacts on the semiconductor chip and the corresponding ones on the front face of the intermediate ceramic substrates are connected by solder. The contacts on the back face of the intermediate ceramic substrate and the corresponding contacts on the front face of the multi-layered ceramic circuit board are connected by respective conductive pins having a predetermined flexibility and rigidity through a predetermined gap therebetween. With this arrangement, the relative displacement due to a thermal expansion difference between the intermediate ceramic substrate and the multi-layered organic circuit board is permitted without causing substantial stress thereon.

公开(公告)号：US4604677A

公开(公告)日：1986-08-05

申请号：US525250

申请日：1983-08-16

Applicant: Go Suzuki ,  Kazuo Michisita

Inventor： Go Suzuki ,  Kazuo Michisita

IPC: H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/00 ,  H05K1/03 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K1/147 ,  H01L21/4867 ,  H01L23/13 ,  H01L23/49805 ,  H01L23/49861 ,  H01L23/5385 ,  H01L25/105 ,  H01L25/16 ,  H05K1/141 ,  H05K3/0014 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/1627 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/0284 ,  H05K1/0306 ,  H05K1/183 ,  H05K2201/045 ,  H05K2201/10477 ,  H05K2203/302 ,  H05K3/3442 ,  H05K3/368 ,  Y10T29/49126 ,  Y10T29/4913

Abstract: A ceramic structural body having electronic components thereon comprises a ceramic package of a ceramic layer having substantially uniform thickness. The package comprises a ceramic element of dish-shaped or box-shaped configuration including a base portion, a sidewall portion extending from the base portion substantially at right angles thereto and a flange portion extending from the free end of the sidewall portion substantially at right angles thereto. The ceramic package is formed by press-forming a ceramic green sheet having substantially uniform thickness. A plurality of metal layers are provided on the surface of desired portions of the ceramic element.

Abstract translation: 其上具有电子部件的陶瓷结构体包括具有基本均匀厚度的陶瓷层的陶瓷封装。 该包装包括一种盘形或箱形结构的陶瓷元件，其包括基部，从基部大致直角延伸的侧壁部分和从侧壁部分的自由端基本直角延伸的凸缘部分 到此。 通过压制形成具有基本均匀厚度的陶瓷生片来形成陶瓷封装。 在陶瓷元件的所需部分的表面上设置多个金属层。

公开(公告)号：US20180054893A1

公开(公告)日：2018-02-22

申请号：US15264613

申请日：2016-09-14

Applicant: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED ,  Lite-On Technology Corporation

Inventor： Yi-Hsun Lee ,  Chun-Lung Ho ,  Wu-Chen Lin

IPC: H05K1/14 ,  H05K1/11

CPC classification number: H05K1/142 ,  H05K1/111 ,  H05K2201/045 ,  H05K2201/048 ,  H05K2201/09027 ,  H05K2201/094 ,  H05K2201/09727

Abstract: A circuit board structure includes a first circuit board, a second circuit board and a plurality of first connection portions. The first circuit board has a first opening, and the second circuit board is disposed inside the first opening of the first circuit board. The first circuit board and the second circuit board are electrically independent from each other. The first connection portions are connected to the first circuit board and the second circuit board.

公开(公告)号：US20170290158A1

公开(公告)日：2017-10-05

申请号：US15085080

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Jeffrey A. Pihlman ,  John C. Tomlin

IPC: H05K1/18 ,  H05K1/11 ,  H01L23/498 ,  H05K3/40 ,  H05K3/10 ,  H05K3/34 ,  H05K1/02 ,  H05K1/14

CPC classification number: H05K1/181 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/50 ,  H01R12/727 ,  H05K1/0262 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/113 ,  H05K1/14 ,  H05K1/141 ,  H05K1/144 ,  H05K3/10 ,  H05K3/341 ,  H05K3/4007 ,  H05K2201/041 ,  H05K2201/042 ,  H05K2201/045 ,  H05K2201/10037 ,  H05K2201/10734 ,  H05K2201/2036

Abstract: IC device assemblies including a power delivery bus board that is mounted to a primary PCB (i.e., motherboard) that further hosts a power-sink device and a power-source device. The bus board, as a secondary PCB, may be surface-mounted on a back side of the primary PCB opposite the power source and sink devices, which are mounted on the front side of the primary PCB. The bus board need only be dimensioned so as to bridge a length between first and second back-side regions of the primary PCB that are further coupled to a portion of the front-side pads employed by the power-sink device. The secondary PCB may be purpose-built for conveying power between the source and sink devices, and include, for example, short, wide traces, that may be formed from multiple heavyweight metallization layers.

公开(公告)号：US09756754B2

公开(公告)日：2017-09-05

申请号：US15083300

申请日：2016-03-29

Applicant: DELTA ELECTRONICS, INC.

Inventor： Tsung-Tai Cheng

IPC: H02M1/36 ,  H05K7/14 ,  H05K5/00 ,  H05K5/02 ,  H05K7/06 ,  H05K1/18

CPC classification number: H05K7/1427 ,  H05K1/141 ,  H05K1/181 ,  H05K5/0069 ,  H05K5/0247 ,  H05K7/06 ,  H05K2201/042 ,  H05K2201/045 ,  H05K2201/10053 ,  H05K2201/10151 ,  H05K2201/10166 ,  H05K2201/10174 ,  H05K2201/10303 ,  H05K2201/10318

Abstract: An integrated power module packaging structure includes a housing, a first circuit board, a second circuit board, a first pin, a second pin and a third pin. The housing has a cavity. The second circuit board is located above the first circuit board, and both them are received in the cavity. A switching module is disposed on the first circuit board. A high side current/voltage detecting device and a driving device are disposed on the second circuit board. The first pin, the second pin and the third pin are disposed between the first circuit board and the second circuit board. The first pin connects the high side current/voltage detecting device and the switching module in series. The second pin connects the switching module. The driving device controls the switching module through the third pin.

公开(公告)号：US20170019998A1

公开(公告)日：2017-01-19

申请号：US14801422

申请日：2015-07-16

Applicant: Delphi Technologies, Inc.

Inventor： Rodrigo Franco

IPC: H05K1/14 ,  H05K1/11 ,  H05K3/40 ,  H05K3/36 ,  H05K3/42 ,  H05K1/18 ,  H05K3/32

CPC classification number: H05K1/144 ,  H05K1/111 ,  H05K1/115 ,  H05K1/14 ,  H05K1/141 ,  H05K1/145 ,  H05K1/181 ,  H05K1/183 ,  H05K3/32 ,  H05K3/3442 ,  H05K3/36 ,  H05K3/4007 ,  H05K3/429 ,  H05K2201/045 ,  H05K2201/09036 ,  H05K2201/09181 ,  H05K2201/095 ,  H05K2201/10166 ,  H05K2201/10727

Abstract: The circuit board assembly includes a first circuit board having a first plurality of electronic components attached to a major surface of the first circuit board. The first plurality of electronic components is electrically interconnected to a first plurality of conductive pads defined on the major surface of the first circuit board. A second circuit board has a second plurality of electronic components attached to a first major surface of the second circuit board. The second plurality of electronic components is electrically interconnected to a second plurality of conductive pads defined on a second major surface of the second circuit board. The first and second circuit board are attached by coupling the first and second plurality of conductive pads. A portion of the first plurality of electronic components on the first circuit board are disposed within a cavity defined by the second major surface of the second circuit board.

Abstract translation: 电路板组件包括具有附接到第一电路板的主表面的第一多个电子部件的第一电路板。 第一组多个电子部件电连接到限定在第一电路板的主表面上的第一多个导电焊盘。 第二电路板具有附接到第二电路板的第一主表面的第二多个电子部件。 所述第二多个电子部件电连接到限定在所述第二电路板的第二主表面上的第二多个导电焊盘。 第一和第二电路板通过联接第一和第二多个导电焊盘而附接。 第一电路板上的第一多个电子部件的一部分设置在由第二电路板的第二主表面限定的空腔内。

公开(公告)号：US20140312488A1

公开(公告)日：2014-10-23

申请号：US14230188

申请日：2014-03-31

Applicant: FUJITSU LIMITED

Inventor： Takashi FUKUDA

IPC: H01L23/00

CPC classification number: H01L23/3128 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0234 ,  H05K1/0286 ,  H05K1/0295 ,  H05K1/113 ,  H05K1/167 ,  H05K2201/045 ,  H05K2201/09381 ,  H05K2201/10159 ,  H05K2201/10378 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing a wiring board unit, the wiring board unit including a semiconductor package that includes a memory chip, a wiring board on which the semiconductor package is mounted, and an insertion base inserted between the wiring board and the semiconductor package, the method includes: forming a plurality of connection portion groups in a base material, the connection portion groups each including a plurality of connection portions that each electrically connect a board-side pad of the wiring board and an external terminal of the semiconductor package to each other; forming the insertion base such that resistances of the connection portions included in the connection portion groups are adjusted in accordance with types of target memory chips; and connecting the external terminals and the board-side pads to one another by using the connection portion group selected in accordance with the type of the memory chip.

Abstract translation: 一种制造布线基板单元的方法，所述布线基板单元包括半导体封装，其包括存储芯片，安装有所述半导体封装的布线基板和插入在所述布线板和所述半导体封装之间的插入基板，所述方法 包括：在基材中形成多个连接部分组，所述连接部分包括多个连接部分，每个连接部分将所述布线板的板侧焊盘和所述半导体封装的外部端子彼此电连接; 形成插入基座，使得包括在连接部分组中的连接部分的电阻根据目标存储芯片的类型进行调节; 以及通过使用根据存储芯片的类型选择的连接部分组将外部端子和电路板侧焊盘彼此连接。