公开(公告)号：US20090025204A1

公开(公告)日：2009-01-29

申请号：US12242252

申请日：2008-09-30

Applicant: Roy Greeff

Inventor： Roy Greeff

IPC: H01P11/00 ,  H05K3/36

CPC classification number: H01P3/081 ,  H05K1/024 ,  H05K3/28 ,  H05K2201/09236 ,  Y10T29/49016 ,  Y10T29/49155

Abstract: A printed circuit board has a dielectric constant different from the dielectric constant of free space, with at least two microstrip lines routed adjacent to one another on a surface of the printed circuit board. A dielectric coating is applied to at least one of the at least two microstrip lines such that the dielectric constant of the dielectric coating differs from the dielectric constant of free space. In a further embodiment, the dielectric coating comprises a material having a dielectric constant approximately equal to the dielectric constant of the printed circuit board.

Abstract translation: 印刷电路板具有与自由空间的介电常数不同的介电常数，至少两条微带线在印刷电路板的表面上彼此相邻布置。 将介电涂层施加到至少两条微带线中的至少一条，使得介电涂层的介电常数与自由空间的介电常数不同。 在另一实施例中，电介质涂层包括介电常数近似等于印刷电路板的介电常数的材料。

公开(公告)号：US20090020323A1

公开(公告)日：2009-01-22

申请号：US12218891

申请日：2008-07-18

Applicant: Chien-Te Chen ,  Ke-Chuan Yang ,  Hung-Ming Chang

Inventor： Chien-Te Chen ,  Ke-Chuan Yang ,  Hung-Ming Chang

IPC: H05K1/09 ,  H05K3/10

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/114 ,  H05K3/108 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/09436 ,  H05K2203/025 ,  H05K2203/0733 ,  Y10T29/49149 ,  H01L2924/00

Abstract: A circuit board structure and a method for fabricating the same are disclosed, including providing a core board having conductive traces and solder pads respectively formed thereon, wherein width of the solder pads corresponds to that of the conductive traces, and pitch between adjacent solder pads is made wide enough to allow multiple conductive traces to pass through; forming on the core board an insulating layer with openings for exposing the solder pads therefrom; forming on the insulating layer a plurality of extending pads electrically connected to the solder pads respectively, wherein the projection area of the extending pads is larger than that of the corresponding solder pads and covers conductive traces adjacent to the corresponding solder pads. Thus, more conductive traces are allowed to pass between adjacent solder pads and meanwhile, the extending pads provide an effective solder ball wetting area for achieving good solder joints and sufficient height after collapse.

Abstract translation: 公开了一种电路板结构及其制造方法，包括提供具有分别形成在其上的导电迹线和焊盘的芯板，其中焊盘的宽度对应于导电迹线的宽度，相邻焊盘之间的间距是 足够宽以允许多个导电迹线通过; 在所述芯板上形成具有用于从其露出焊盘的开口的绝缘层; 在所述绝缘层上形成分别电连接到所述焊盘的多个延伸焊盘，其中所述延伸焊盘的所述投影区域大于相应焊接焊盘的所述投影区域并且覆盖与相应焊盘相邻的导电迹线。 因此，允许更多的导电迹线在相邻焊盘之间通过，同时，延伸焊盘提供有效的焊球润湿区域，以实现良好的焊点和崩溃后的足够的高度。

公开(公告)号：US20090016031A1

公开(公告)日：2009-01-15

申请号：US12144595

申请日：2008-06-23

Applicant: Shoji Matsumoto

Inventor： Shoji Matsumoto

IPC: H05K1/18 ,  H05K1/00

CPC classification number: H05K1/0224 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/0969 ,  H05K2201/09727

Abstract: While gradually increasing the widths of signal lines (104a, 104b, 105a, 105b) of first and second groups of differential signal lines (104, 105) to suppress attenuation in the lines, the opening widths of slits (104s, 105s) formed in a GND layer (102) below the differential signal lines are similarly changed. Thereby, impedance matching is realized. Further, by alternately disposing a large-width side and a small-width side of the two groups of differential signal lines (104, 105), the total wiring area widths are reduced.

Abstract translation: 在逐渐增加第一组和第二组差分信号线（104,105）的信号线（104a，104b，105a，105b）的宽度以抑制线中的衰减的同时，形成的狭缝（104s，105s）的开口宽度 类似地，差分信号线下面的GND层（102）也被改变。 从而实现阻抗匹配。 此外，通过交替地设置两组差分信号线（104,105）的大宽度侧和小宽度侧，总布线面积宽度减小。

公开(公告)号：US20090008148A1

公开(公告)日：2009-01-08

申请号：US12165885

申请日：2008-07-01

Applicant: Naohiro Mashino

Inventor： Naohiro Mashino

IPC: H05K9/00

CPC classification number: H05K1/0219 ,  H01F2017/008 ,  H05K1/0218 ,  H05K1/165 ,  H05K2201/09236 ,  H05K2201/09972 ,  H05K2201/10371

Abstract: There is provided a wiring board having a shield function. The wiring board includes: a plurality of conductive shield patterns adapted to surround a circumference of at least one electronic component mounting area on the wiring board, the plurality of conductive shield patterns being adjacent to each other; and at least one inductor formed of a conductive pattern and provided between the conductive shield patterns.

Abstract translation: 提供了具有屏蔽功能的布线板。 所述布线板包括：多个导电屏蔽图形，其适于围绕所述布线板上的至少一个电子部件安装区域的圆周，所述多个导电屏蔽图案彼此相邻; 以及由导电图案形成的至少一个电感器，并设置在导电屏蔽图案之间。

公开(公告)号：US20080296048A1

公开(公告)日：2008-12-04

申请号：US12114455

申请日：2008-05-02

Applicant: Kiyomi Muro ,  Akihiko Happoya

Inventor： Kiyomi Muro ,  Akihiko Happoya

IPC: H05K1/00

CPC classification number: H05K1/0218 ,  H05K1/0237 ,  H05K1/0393 ,  H05K3/4664 ,  H05K2201/0715 ,  H05K2201/09236

Abstract: A flexible printed circuit board includes: a base film that has electrical insulation property; a conductive pattern that is formed on the base film and including a pair of differential signal lines and a ground line; an insulating layer that is formed on the conductive pattern; a conductive layer that is formed on the insulating layer; and a connecting portion that electrically connects the ground line and the conductive layer through a penetration hole formed on the insulating layer.

Abstract translation: 柔性印刷电路板包括：具有电绝缘性能的基膜; 导电图案，其形成在所述基底膜上并且包括一对差分信号线和接地线; 形成在所述导电图案上的绝缘层; 形成在所述绝缘层上的导电层; 以及连接部，其通过形成在所述绝缘层上的贯通孔将所述接地线与所述导电层电连接。

公开(公告)号：US20080290495A1

公开(公告)日：2008-11-27

申请号：US12068606

申请日：2008-02-08

Applicant: Yutaka Uematsu ,  Tatsuya Saito ,  Hideki Osaka ,  Yoji Nishio ,  Shunichi Saito

Inventor： Yutaka Uematsu ,  Tatsuya Saito ,  Hideki Osaka ,  Yoji Nishio ,  Shunichi Saito

IPC: H01L23/528

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/09 ,  H05K1/111 ,  H05K1/167 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09781 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

Abstract: As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.

Abstract translation: 作为半导体芯片中的馈电路径，可以实现降低数十MHz频率范围内的反谐振阻抗的馈电路径，从而抑制半导体器件的功率噪声。 通过插入将中频带中的电阻提升到电阻本身较高的部分的结构，例如半导体封装中的功率布线和电容器互连电极部件，可以有效地减少中频带中的反谐振阻抗，同时保持 阻抗低在低频。

公开(公告)号：US20080285245A1

公开(公告)日：2008-11-20

申请号：US11749752

申请日：2007-05-17

Applicant: Ting-Hao Lin ,  Chien-Wei Chang

Inventor： Ting-Hao Lin ,  Chien-Wei Chang

IPC: H05K1/18 ,  H01S4/00

CPC classification number: H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/108 ,  H05K3/205 ,  H05K2201/09236 ,  H05K2201/09881 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: Embedded passive device structure and its manufacturing method for mainly embedding the passive device structure in the printed circuit board are presented. In this structure, both the source electrode and the ground electrode of the passive device belong to the same level, and includes several source branches and several ground branches that are formed vertically on the inside of the dielectric layer of the circuit board which are connected, respectively, to avoid the conducting between the source electrode and the ground electrode during lamination. When it is in the form of the capacitor structure, through the use of the ultra-fine wiring technique, these source branches and ground branches are separated by a small gap between each other. Therefore, the side face area and quantities of the source branches and ground branches are both increased.

Abstract translation: 介绍了嵌入式无源器件结构及其主要将无源器件结构嵌入印刷电路板的制造方法。 在该结构中，无源器件的源电极和接地电极都属于同一水平，并且包括垂直形成在电路板的电介质层的内部上的多个源极分支和几个接地分支， 以避免在层压期间源电极和接地电极之间的导电。 当它是电容器结构的形式时，通过使用超细布线技术，这些源极分支和接地分支之间彼此间有很小的间隙。 因此，源分支和接地分支的侧面积和数量都增加。

公开(公告)号：US20080283286A1

公开(公告)日：2008-11-20

申请号：US12019661

申请日：2008-01-25

Applicant: Mitsuru Honjo

Inventor： Mitsuru Honjo

IPC: H05K1/11 ,  H05K1/00

CPC classification number: H05K1/0218 ,  H05K1/0216 ,  H05K1/162 ,  H05K3/4664 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09727

Abstract: A printed circuit board includes a base insulating layer, first to third signal lines, a first cover insulating layer and a conductive layer. Wide parts are formed in the first to third signal lines. The first cover insulating layer is provided on the base insulating layer so as to cover the wide parts. The conductive layer is provided on the first cover insulating layer so as to cover a portion above the wide parts.

Abstract translation: 印刷电路板包括基底绝缘层，第一至第三信号线，第一覆盖绝缘层和导电层。 在第一至第三信号线中形成宽部分。 第一覆盖绝缘层设置在基底绝缘层上以覆盖宽部分。 导电层设置在第一覆盖绝缘层上，以覆盖宽部分上方的部分。

公开(公告)号：US20080265411A1

公开(公告)日：2008-10-30

申请号：US11979980

申请日：2007-11-13

Applicant: Wen-Hung Hu

Inventor： Wen-Hung Hu

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H05K3/3452 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2924/00014 ,  H05K1/112 ,  H05K2201/09236 ,  H05K2201/09436 ,  H05K2201/09854 ,  H05K2203/054 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A structure of a packaging substrate and a method for making the same are disclosed, wherein the structure comprises: a substrate body having a circuit layer on the surface thereof, wherein the circuit layer has a plurality of conductive pads which are each formed in a flat long shape to enhance the elasticity of circuit layout; a solder mask disposed on the substrate body and having a plurality of openings corresponding to and exposing the conductive pads, wherein the openings are each formed in a flat long shape; and a metal bump disposed in each of the openings of the solder mask and on each of the corresponding conductive pads.

Abstract translation: 公开了一种封装基板的结构及其制造方法，其特征在于，所述结构体包括：表面具有电路层的基板主体，其中，所述电路层具有多个导电焊盘， 长形增强电路布局的弹性; 焊接掩模，其设置在所述基板主体上并且具有对应于并暴露所述导电焊盘的多个开口，其中所述开口各自形成为平坦的长形状; 以及设置在焊料掩模的每个开口中和每个相应导电焊盘上的金属凸块。

公开(公告)号：US20080250377A1

公开(公告)日：2008-10-09

申请号：US11696659

申请日：2007-04-04

Applicant: Steven C. Bird ,  Varoujan Malian ,  Mudasir Ahmad ,  Charles H. Casale ,  Danlu Tang

Inventor： Steven C. Bird ,  Varoujan Malian ,  Mudasir Ahmad ,  Charles H. Casale ,  Danlu Tang

IPC: G06F17/50 ,  G01R31/00

CPC classification number: G01R31/2818 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/0262 ,  H05K1/0268 ,  H05K1/113 ,  H05K1/181 ,  H05K3/3421 ,  H05K3/3457 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/0367 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/09663 ,  H05K2201/10333 ,  H05K2201/10462 ,  H05K2201/10484 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611

Abstract: Methods and apparatus for accessing a high speed signal routed on a conductive trace on an internal layer of a printed circuit board (PCB) using high density interconnect (HDI technology) are provided. The conductive trace may be coupled to a microvia (μVia) having a conductive dome disposed above the outer layer pad of the μVia. In-circuit test (ICT) fixtures or high speed test probes may interface with the conductive dome to test the high speed signal with decreased reflection loss and other parasitic effects when compared to conventional test points utilizing plated through-hole (PTH) technology.

Abstract translation: 提供了使用高密度互连（HDI技术）访问在印刷电路板（PCB）的内层上的导电迹线上路由的高速信号的方法和装置。 导电迹线可以耦合到具有设置在muVia的外层焊盘上方的导电圆顶的微孔（muVia）。 与使用电镀通孔（PTH）技术的常规测试点相比，在线测试（ICT）固定装置或高速测试探头可与导电圆顶接口以测试具有降低的反射损耗和其他寄生效应的高速信号。